An Experimental Full-CMOS Multigigahertz PLL LSI Using 0.4μm Gate Ultrathin-Film SIMOX Technology (Special Issue on Sub-Half Micron Si Device and Process Technologies)
スポンサーリンク
概要
- 論文の詳細を見る
We designed and fabricated a prototype 0.4-μm-gate CMOS / SIMOX PLL LSI in order to verify the potential usefulness of ultrathin-film SIMOX technology for creating an extremely low-power LSI containing high-speed circuits operating at frequencies of at least 1 GHz and at low supply voltages. This PLL LSI contains both high-frequency components such a prescaler and low-frequency components such as a shift register, phase frequency comparator, and fixed divider. One application of the LSI could be for synthesizing communication band frequencies in the front-end of a battery-operated wireless handy terminal for personal communications. At a supply voltage of 2 V, this LSI operates at up to 2 GHz while dissipating only 8.4 mW. Even at only 1.2 V, 1 GHz-operation can be obtained with a power consumption of merely 1.4 mW. To explain this low-power feature, we extensively measured the electrical characteristics of individual CMOS / SIMOX basic circuits as well as transistors. Test results showed that the high performance of the LSI is mainly due to the advanced nature of the CMOS / SIMOX devices with low parasitic capacitances around source / drain regions and to the new circuit design techniques used in the dual-modulus prescalar.
- 社団法人電子情報通信学会の論文
- 1993-04-25
著者
-
KADO Yuichi
NTT Microsystem Integration Laboratories, NTT Corporation
-
Omura Y
Electronics High-technology Research Center And Faculty Of Engineering Kansai University
-
Omura Y
Ntt Lsi Laboratories
-
Omura Yasuhisa
Electronics Department Kansai University
-
Omura Yasuhisa
NTT LSI Laboratories
-
Suzuki M
Kddi Res. And Dev. Lab. Inc. Kamifukuoka‐shi Jpn
-
Suzuki Masao
NTT LSI Laboratories
-
Kado Yuichi
NTT LSI Laboratories
-
Koike Keiichi
NTT LSI Laboratories
-
Izumi Katsutoshi
NTT LSI Laboratories
-
Kado Yuichi
Ntt Microsystem Integration Laboratories
-
Kado Yuichi
Ntt Microsystem Integration Laboratories Ntt Corporation
-
Koike K
Ntt Systems Electronics Lab. Atsugi‐shi Jpn
関連論文
- A1-V Cyclic A/D Converter Using FD-SOI Sample/Hold Circuits for Sensor Networks(Analog, Low-Power LSI and Low-Power IP)
- A Low Power Multiplier Using Adiabatic Charging Binary Decision Diagram Circuit
- Low-Temperature Drain Current Characteristics in Sub-10-nm-Thick SOI nMOSFET's on SIMOX (Separation by IMplanted OXygen) Substrates
- Abnormal Threshold Voltage Dependence on Gate Length in Ultrathin-Film n-Channel Metal-Oxide-Semiconductor Field-Effect Transistors (nMOSFET's) Using Separation by Implanted Oxygen (SIMOX) Technology
- An FFT Interference Detection Scheme for Interference Suppression in Digital Satellite Communication Systems
- An Integrated Interference Suppression Scheme with An Adaptive Equalizer for Digital Satellite Communication Systems
- 10 Gbit / s, 35mV Decision IC Using 0.2μm GaAs MESFETs (Special Section of Letters Selected from the '92 Fall Conference and the '93 Spring Conference)
- A 1GHz/0.9mW CMOS/SIMOX Divide-by 128/129 Dual-Modulus Prescaler Using a Divide-by 2/3 Synchronous Counter
- An Experimental Full-CMOS Multigigahertz PLL LSI Using 0.4μm Gate Ultrathin-Film SIMOX Technology (Special Issue on Sub-Half Micron Si Device and Process Technologies)
- Influence of Doping Gradient near a Channel End on Parasitic Series Resistance of Thin-Film Fully-Depleted Metal-Oxide-Semiconductor Field-Effect Transistors
- Body-Charge-Induced Switching Characteristics in Fully Depleted Silicon-on-Insulator Digital Circuits
- 300-kilo-Gate Sea-of-Gate Type Gate Arrays Fabricated Using 0.25-μm-Gate Ultra-Thin-Film Fully-Depleted Complementary Metal-Oxide-Semiconductor Separation by IMplanted OXygen (CMOS/SIMOX) Technology with Tungsten-Covered Source and Drain
- Design of the Basic Cell and Metallized RAM for 0.5μm CMOS Gate Array
- Single-Mode Silicon Optical Switch with T-Shaped SiO_2 Optical Waveguide as a Control Gate
- Study on Silicon Optical Switch with T-Shape SiO_2 Waveguide as an Optical Control Gate
- Two-Dimensionally Confined Carrier Injection Phenomena in Sub-10-nm-Thick SOI Insulated-Gate pn-Junction Devices
- A 4:1 MUX Circuit Using 1/4 Micron CMOS/SIMOX for High-Speed and Low-Power Applications
- 3-Gb/s CMOS 1:4 MUX and DEMUX ICs
- Quantum Mechanical Influence on Flat-Band Capacitance for Metal-Oxide-Semiconductor Structures with Nanometer-Thick Silicon Oxide Film and the Impact of Oxide Charge Evaluation
- Quantum mechanical effect in temperature dependence of threshold voltage of extremely thin SOI MOSFETs
- Quantization Effect in Temperature Dependence of Threshold Voltage of Extremely-Thin SOI MOSFETs
- 8-mW,1-V,100-Msample/s,6-bit A/D Converter Using a Latched Comparator Operating in the Triode Region
- A Low Power Multiplier Using Adiabatic Charging Binary Decision Diagram Circuit
- Millimeter-wave MMIC Technologies Exploring F-band Application(Session7: Millimeter-wave and Terahertz Devices)
- Millimeter-wave MMIC Technologies Exploring F-band Application(Session7: Millimeter-wave and Terahertz Devices)
- Physics-based model of quantum-mechanical wave function penetration into thin dielectric films for evaluating modern MOS capacitors
- Effect of Silicon Addtion on Electrical Properties of SrBi2Ta2O9 Thin Films
- Effect of Silicon Addition on Electrical Properties of SrBi_2Ta_2O_9 Thin Films
- A Partial-Ground-Plane (PGP) Silicon-on-Insulator (SOI) Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) for Deep Sub-0.1μm Channel Regime
- Proposal of a Partial-Ground-Plane (PGP) Silicon-on-Insulator (SOI) MOSFET for Deep sub-0.1-μm Channel Regime
- Proposal of a Partial-Ground-Plane(PGP) Silicon-on-Insulator(SOI) MOSFET for Deep Sub-100-nm Channel Regime
- Physical and Mathematical Basis for the Crucial Technical Shortcoming of the Split C-V Technique in Thin-SOI MOSFET's
- Enhancement and Suppression of Band-to-Band Tunneling Current in Ultra-Thin nMOSFETs/SIMOX : Influence of Superficial Si Layer Thickness and It's Future Prospect
- Dependence of CMOS/SIMOX Inverter Delay Time on Gate Overlap Capacitance
- A Simple Model for Substrate Current Characteristics in Short-Channel Ultrathin-Film Metal-Oxide-Semiconductor Field-Effect Transistors by Separation by Implanted Oxygen
- A 4:1 MUX Circuit Using 1/4 Micron CMOS/SIMOX for High-Speed and Low-Power Applications