8-mW,1-V,100-Msample/s,6-bit A/D Converter Using a Latched Comparator Operating in the Triode Region
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概要
- 論文の詳細を見る
A very low-power, high-speed flash A/D converter front-end composed of a new latched comparator was developed. We established a butterfly sorting technique to guarantee the monotonicity of the converter. The 6-bit A/D front-end achieves a speed of 100Msps and dynamic range of 33dB wit power consumption of only 7mW at the supply voltage of 1V, and the butterfly sorter guarantees 6-bit monotonicity with an extra power consumption of 1 mW.
- 社団法人電子情報通信学会の論文
- 2003-02-01
著者
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TERADA Jun
NTT Microsystem Integration Laboratories, NTT Corporation
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MATSUYA Yasuyuki
NTT Microsystem Integration Laboratories, NTT Corporation
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KADO Yuichi
NTT Microsystem Integration Laboratories, NTT Corporation
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Terada Jun
Ntt Microsystem Integration Laboratories Ntt Corporation
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Kado Yuichi
Ntt Microsystem Integration Laboratories
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Kado Yuichi
Ntt Micro System Integration Laboratories
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Kado Yuichi
Ntt Microsystem Integration Laboratories Ntt Corporation
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MORISAWA Fumiharu
NTT Microsystem Integration Labs.,NTT Corporation
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Matsuya Y
Ntt Microsystem Integration Laboratories Ntt Corporation
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Morisawa Fumiharu
Ntt Microsystem Integration Labs. Ntt Corporation
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Terada Jun
Ntt Microsystem Integration Laboratories Ntt Corp.
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