A Low Power Multiplier Using Adiabatic Charging Binary Decision Diagram Circuit
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概要
- 論文の詳細を見る
- 社団法人応用物理学会の論文
- 2000-04-30
著者
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Yamada J
Laboratory Of Anatomy Department Of Basic Veterinary Science Obihiro University Of Agriculture And V
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KADO Yuichi
NTT Microsystem Integration Laboratories, NTT Corporation
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Nakata Shunji
Ntt Telecommunications Energy Laboratories
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Yamada Junzo
Ntt Telecommunications Energy Laboratories
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Yamada Junzo
Ntt Technology Research Department
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DOUSEKI Takakuni
NTT Telecommunications Energy Laboratories
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KADO Yuichi
NTT Telecommunications Energy Laboratories
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Douseki T
Ntt Corp. Atsugi‐shi Jpn
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Kado Yuichi
Ntt Microsystem Integration Laboratories
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Kado Yuichi
Ntt Microsystem Integration Laboratories Ntt Corporation
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Nakata S
Ntt Telecommunications Energy Laboratories
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