Energy-Reduction Effect of Ultralow-Voltage MTCMOS / SIMOX Circuits Using a Graph with Equispeed and Equienergy Lines (Special Issue on Low-Power High-Speed CMOS LSI Technologies)

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概要

• 論文の詳細を見る

• This paper describes the effect of lowering the supply voltage and threshold voltages on the energy reduction of an ultralow-voltage multi-threshold CMOS / SIMOX (MTC-MOS / SIMOX) circuit. The energy dissipation is evaluated using a graph with equispeed and equienergy lines on a supply voltage and a threshold voltage plane. In order to draw equispeed and equienergy lines for ultralow-voltage circuits, we propose a modified energy-evaluation model taking into account a input-waveform transition-time of the circuits. The validity of the proposed energy-evaluation model is confirmed by the evaluation of a gate-chain TEG and a 16-bit CLA adder fabricated with 0.25-μm MTCMOS / SIMOX technology. Using the modified model, the energy-reduction effect in lowering the supply voltage is evaluated for a single-V_<th> fully-depleted CMOS / SOI circuit, a dual-V_<th> CMOS circuit consisting of fully-depleted low- and medium-V_<th> MOSFETs, and a triple-V_<th> MTCMOS / SIMOX circuit. The evaluation reveals that lowering the supply voltage of the MTCMOS / SIMOX circuit to 0.5 V is advantageous for the energy reduction at a constant operating speed.

• 社団法人電子情報通信学会の論文
• 2000-02-25

著者

• Yamada J

  Ntt Telecommunications Energy Laboratories

• Yamada Junzo

  Ntt Telecommunications Energy Laboratories

• Yamada Junzo

  Ntt Technology Research Department

• DOUSEKI Takakuni

  NTT Telecommunications Energy Laboratories

• SHIMAMURA Toshishige

  NTT Telecommunications Energy Laboratories

• FUJII Koji

  NTT Telecommunications Energy Laboratories

関連論文

• Energy-Reduction Effect of Ultralow-Voltage MTCMOS / SIMOX Circuits Using a Graph with Equispeed and Equienergy Lines (Special Issue on Low-Power High-Speed CMOS LSI Technologies)
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• A 0.5-V, Over 1-GHz, 1-mW MUX/DEMUX Core with Multi-Threshold Zero-Vth CMOS/SIMOX Technology
• A Low Power Multiplier Using Adiabatic Charging Binary Decision Diagram Circuit
• Low Voltage SOI Circuit Technology

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