Evaluation of Soft-Error Immunity for 1-V CMOS Memory Cells with MTCMOS Technology (Special Issue on Microelectronic Test Structure)
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概要
- 論文の詳細を見る
Soft-error immunity of a 1-V operating CMOS memory cell is described. To evaluate the immunity precisely at the supply voltage of 1 V, a multi-threshold CMOS (MTCMOS) memory scheme, which has a peripheral circuit combining low-threshold CMOS logic gates and high-threshold MOSFETs with a virtual supply line, is adopted as a test structure. A 1-kb memory was designed and fabricated with 0.5-μm MTCMOS technology and the soft-error immunity of the memory cells was evaluated. The results of an alpha-particle exposure test and a pulse laser test show that a full-CM0S memory cell has high immunity at 1-V operations.
- 社団法人電子情報通信学会の論文
- 1996-02-25
著者
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Yamada Junzo
Ntt Telecommunications Energy Laboratories
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Yamada Junzo
Ntt Technology Research Department
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DOUSEKI Takakuni
NTT LSI Laboratories
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UEKI Takemi
NTT LSI Laboratories
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Douseki T
Ntt Corp. Atsugi‐shi Jpn
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Mutoh Shin'ichiro
Ntt Lsi Laboratories
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