A 1-V MTCMOS Circuit Hardened to Temperature-Dependent Delay-Time Variation

スポンサーリンク

概要

• 論文の詳細を見る

• This paper describes the effects of operating temperature on delay time in a 1-V multi-threshold CMOS (MTCMOS) circuit. Delay-time analysis including the temperature factor shows that the delay-time variation of the CMOS circuit becomes small for low-voltage operation and the variation is mainly determined by the threshold voltage and its variation-rate with temperature. As a design method of a MTCMOS circuit with both high-threshold and low-threshold MOSFETs, optimization of the low-threshold voltage at which the delay-time of the circuit is independent of operating temperature is described in detail. The validity of the design method is confirmed by the evaluation of a gate-chain TEG and a 1-V 12 K-gate digital-filter LSI fabricated with 0.5-μm MTCMOS technology.

• 社団法人電子情報通信学会の論文
• 1996-08-25

著者

• DOUSEKI Takakuni

  NTT LSI Laboratories

• Mutoh Shin-ichiro

  Ntt Lsi Laboratories

関連論文

• Evaluation of Soft-Error Immunity for 1-V CMOS Memory Cells with MTCMOS Technology (Special Issue on Microelectronic Test Structure)
• A 1-V MTCMOS Circuit Hardened to Temperature-Dependent Delay-Time Variation
• A High-Speed Feed-Forward BiNMOS Driver for Low-Voltage LSIs (Special Section on Low-Power and Low-Voltage Integrated Circuits)
• Analysis of P^+ -n Junction Capacitance with Three-Dimensional Impurity Profiling Method Using Scanning Tunneling Microscopy
• Dependence of CMOS/SIMOX Inverter Delay Time on Gate Overlap Capacitance

スポンサーリンク