A1-V Cyclic A/D Converter Using FD-SOI Sample/Hold Circuits for Sensor Networks(Analog, <Special Section>Low-Power LSI and Low-Power IP)
スポンサーリンク
概要
- 論文の詳細を見る
A cyclic A/D conversion circuit technique for sensor networks has been developed using 0.2-μm CMOS/FD-SOI technology. The FD-SOI analog switches can lower the supply voltage without degrading accuracy because of their negligible body effect. The proposed A/D converter achieves operation at the supply voltage of 1 V or less and can handle a sampling frequency ranging from 8 Sps to 8 kSps with a new clocking technique.
- 2005-04-01
著者
-
TERADA Jun
NTT Microsystem Integration Laboratories, NTT Corporation
-
MATSUYA Yasuyuki
NTT Microsystem Integration Laboratories, NTT Corporation
-
MUTOH Shinichiro
NTT Microsystem Integration Laboratories, NTT Corporation
-
KADO Yuichi
NTT Microsystem Integration Laboratories, NTT Corporation
-
Terada Jun
Ntt Microsystem Integration Laboratories Ntt Corporation
-
Kado Yuichi
Ntt Microsystem Integration Laboratories
-
Kado Yuichi
Ntt Micro System Integration Laboratories
-
Kado Yuichi
Ntt Microsystem Integration Laboratories Ntt Corporation
-
Matsuya Y
Ntt Microsystem Integration Laboratories Ntt Corporation
-
Mutoh Shinichiro
Ntt Microsystem Integration Laboratories Ntt Corporation
-
Terada Jun
Ntt Microsystem Integration Laboratories Ntt Corp.
関連論文
- A1-V Cyclic A/D Converter Using FD-SOI Sample/Hold Circuits for Sensor Networks(Analog, Low-Power LSI and Low-Power IP)
- A Low Power Multiplier Using Adiabatic Charging Binary Decision Diagram Circuit
- A 1GHz/0.9mW CMOS/SIMOX Divide-by 128/129 Dual-Modulus Prescaler Using a Divide-by 2/3 Synchronous Counter
- An Experimental Full-CMOS Multigigahertz PLL LSI Using 0.4μm Gate Ultrathin-Film SIMOX Technology (Special Issue on Sub-Half Micron Si Device and Process Technologies)
- Influence of Doping Gradient near a Channel End on Parasitic Series Resistance of Thin-Film Fully-Depleted Metal-Oxide-Semiconductor Field-Effect Transistors
- Body-Charge-Induced Switching Characteristics in Fully Depleted Silicon-on-Insulator Digital Circuits
- 300-kilo-Gate Sea-of-Gate Type Gate Arrays Fabricated Using 0.25-μm-Gate Ultra-Thin-Film Fully-Depleted Complementary Metal-Oxide-Semiconductor Separation by IMplanted OXygen (CMOS/SIMOX) Technology with Tungsten-Covered Source and Drain
- A 4:1 MUX Circuit Using 1/4 Micron CMOS/SIMOX for High-Speed and Low-Power Applications
- 3-Gb/s CMOS 1:4 MUX and DEMUX ICs
- 8-mW,1-V,100-Msample/s,6-bit A/D Converter Using a Latched Comparator Operating in the Triode Region
- A Low Power Multiplier Using Adiabatic Charging Binary Decision Diagram Circuit
- Millimeter-wave MMIC Technologies Exploring F-band Application(Session7: Millimeter-wave and Terahertz Devices)
- Millimeter-wave MMIC Technologies Exploring F-band Application(Session7: Millimeter-wave and Terahertz Devices)
- A 6-bit A/D Converter for MEMS-control circuit
- Digital Correction Technique for Multi-Stage Noise-Shaping with an RC-Analog Integrator (Special Issue on Multimedia, Analog and Processing LSIs)
- A Capacitive Sensing Scheme for Control of Movable Element with Complementary Metal–Oxide–Semiconductor Microelectoromechanical-Systems Device
- An Injection-Controlled 10-Gb/s Burst-Mode CDR Circuit for a 1G/10G PON System
- Influence of Doping Gradient near a Channel End on Parasitic Series Resistance of Thin-Film Fully-Depleted Metal–Oxide–Semiconductor Field-Effect Transistors
- Monolithic Integration Fabrication Process of Thermoelectric and Vibrational Devices for Microelectromechanical System Power Generator
- Body-Charge-Induced Switching Characteristics in Fully Depleted Silicon-on-Insulator Digital Circuits