Body-Charge-Induced Switching Characteristics in Fully Depleted Silicon-on-Insulator Digital Circuits

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概要

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• Switching characteristics of digital circuits built with fully depleted (FD) silicon-on-insulator (SOI) metal–oxide–semiconductor field effect transistors (MOSFETs) are experimentally investigated. The results show that the switching speed depends on the input-signal frequency even in FD SOI digital circuits, though FD SOI MOSFETs are expected to suppress floating body effects. The switching becomes faster as the input-signal frequency decreases. This is because the body charge dynamically changes during the switching even in FD SOI MOSFETs. FD SOI MOSFETs have no neutral region in the body, while partially depleted (PD) MOSFETs do. Therefore, impact ionization plays a major role in changing the body charge in FD SOI MOSFETs, while charge redistribution does in PD SOI MOSFETs. The accumulation of majority carriers generated by impact ionization increases the body charge, and thus thereshold voltage decreases, which causes an excess drain current. This excess current is the reason for the faster switching in FD SOI digital circuits. Since the impact ionization efficiency decreases as the supply voltage decreases, the dependence of propagation delay time, $t_{\text{pd}}$, on the input signal frequency can be largely reduced for FD SOI digital circuits. We also discuss several ways to efficiently decrease majority carriers accumulated in the body region and thereby minimize the dependence of $t_{\text{pd}}$ on the input-signal frequency for FD SOI digital circuits.

• Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physicsの論文
• 2004-08-15

著者

• Nishimura Kazuyoshi

  Ntt Microsystem Integration Laboratories

• SATO Yasuhiro

  NTT Microsystem Integration Laboratories

• ISHIHARA Takako

  NTT Microsystem Integration Laboratories

• Kado Yuichi

  Ntt Micro System Integration Laboratories

• Tsuchiya Toshiaki

  Interdisciplinary Faculty Of Science And Engineering Shimane University

• Nishimura Kazuyoshi

  NTT Microsystem Integration Laboratories, 3-1 Morinosato Wakamiya, Atsugi, Kanagawa 243-0198, Japan

• Ishihara Takako

  NTT Microsystem Integration Laboratories, 3-1 Morinosato Wakamiya, Atsugi, Kanagawa 243-0198, Japan

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