Grain-Boundary Related Hot Carrier Degradation Mechanism in Low-Temperature Polycrystalline Silicon Thin-Film Transistors

概要

論文の詳細を見る
Unique degradation behavior of transfer characteristics was observed in low-temperature (LT) polycrystalline silicon (poly-Si) thin-film transistors (TFTs) after hot carrier stress. In the transfer characteristics, drain current was reduced markedly after stress at a gate voltage ($V_{\text{G}}$) of more than the threshold voltage ($V_{\text{T}}$), while it showed little change after stress at $V_{\text{G}}$ of less than $V_{\text{T}}$. These phenomena cannot be explained by the generation of fixed charges in the gate oxide or gate-oxide interface trap charges. To understand this degradation mechanism, the stress-induced resistance $R_{\text{I}}$ is introduced, which is connected with the channel resistance $R_{\text{channel}}$ in series. The calculated $R_{\text{I}}$ values are systematically decreased with the increase in drain voltage ($V_{\text{D}}$), which indicates that the degraded region is close to the drain edge near the surface. Moreover, $R_{\text{I}}$ values show exponential decay with the increase in $V_{\text{G}}$, which implies the lowering of a potential barrier. A possible origin of $R_{\text{I}}$ is potential barriers caused by negative charges generated at the grain boundaries degraded by hot carrier attack.
2003-04-15