A 10-Gb/s Burst-Mode Clock-and-Data Recovery IC with Frequency-Adjusting Dual Gated VCOs
スポンサーリンク
概要
- 論文の詳細を見る
A high-speed serial, 10-Gb/s, passive optical network (PON) is a good candidate for a future PON system. However, there are several issues to be solved in extending the physical speed to 10Gb/s. The issues focused on here are not only the data rate, which is eight times higher than that of a conventional GE-PON, but also the instantaneous amplification and synchronization of AC-coupling burst-input data without a reset signal. An input amplifier with data-edge detection can both detect levelvarying input due to AC-coupling and respond to the first bit of a burst packet. Another issue discussed here is tolerance to long consecutive identical digits (CIDs). A burst-mode clock-and-data recovery (CDR) using dual gated VCOs (G-VCOs) is designed for 10-Gb/s operation. The relation between the frequency difference of the dual G-VCOs and CID tolerance is derived with a frequency tunable G-VCO circuit. The burst-mode CDR IC is implemented in a 0.13-μm CMOS process. It successfully operates at a data rate of 10.3125Gb/s. The CDR IC using the edge-detection input amplifier and the G-VCO CDR core achieves amplification and synchronization in 0.2ns with AC-coupling without a reset signal. The IC also demonstrates 1001bits of CID tolerance, which is more than enough tolerance for 65-bit CIDs in the 64B/66B code of 10 Gigabit Ethernet. Measured data suggest that dual G-VCOs on a die have over a 20-MHz frequency difference and that the frequency adjusting between the G-VCOs is effective for increasing CID tolerance.
- (社)電子情報通信学会の論文
- 2008-06-01
著者
-
OHTOMO Yusuke
NTT Microsystem Integration Laboratories, NTT Corporation
-
NOGAWA Masafumi
NTT Microsystem Integration Laboratories, NTT Corporation
-
NISHIMURA Kazuyoshi
NTT Microsystem Integration Laboratories, NTT Corporation
-
KIMURA Shunji
NTT Access Network Service Systems Laboratories, NTT Corporation
-
YOSHIDA Tomoaki
NTT Access Network Service Systems Laboratories, NTT Corporation
-
KAWAMURA Tomoaki
NTT Microsystem Integration Laboratories, NTT Corporation
-
TOGASHI Minoru
NTT Microsystem Integration Laboratories, NTT Corporation
-
KUMOZAKI Kiyomi
NTT Access Network Service Systems Laboratories, NTT Corporation
-
Kumozaki Kiyomi
Ntt Access Network Service Systems Laboratories Ntt Corporation
-
Ohtomo Yusuke
Ntt Microsystem Integration Laboratories Ntt Corporation
-
Kimura Shunji
Ntt Access Network Service Systems Laboratories Ntt Corporation
-
Togashi Minoru
Ntt Microsystem Integration Laboratories Ntt Corporation
-
Yoshida Tomoaki
Ntt Access Network Service Systems Laboratories Ntt Corporation
-
Nogawa Masafumi
Ntt Microsystem Integration Laboratories Ntt Corporation
-
Kawamura Tomoaki
Ntt Microsystem Integration Laboratories Ntt Corporation
-
Nishimura Kazuyoshi
Ntt Microsystem Integration Laboratories Ntt Corporation
-
Nishimura Kazuyoshi
Ntt Microsystem Integration Laboratories
-
Ohtomo Yusuke
Ntt Microsystem Integration Laboratories Ntt Corp.
関連論文
- Adaptive Power Saving Mechanism for 10 Gigabit Class PON Systems
- A 10-Gb/s Burst-Mode Clock-and-Data Recovery IC with Frequency-Adjusting Dual Gated VCOs
- Reducing the backreflection impact by using homodyne detection in WDM single-fiber loopback access networks
- Gbit-Class Transmission Using SOA Data Rewriter for WDM-PON
- Adaptive Power Saving Mechanism for 10 Gigabit Class PON Systems
- Gbit-Class Transmission Using SOA Data Rewriter for WDM-PON
- A Security Method for Passive Double Star Optical Access Systems
- B-10-50 Multilevel-based Future Generation PON with Reduced Bandwidth by Employing Adaptive Digital Equalization
- A Compact 16-Channel Integrated Optical Subscriber Module for Economical Optical Access Systems(Fiber-Optic Transmission)
- A 10-Gb/s Burst-Mode Clock-and-Data Recovery IC with Frequency-Adjusting Dual Gated VCOs
- A WDM-Based Future Optical Access Network and Support Technologies for Adapting the User Demands' Diversity
- Body-Charge-Induced Switching Characteristics in Fully Depleted Silicon-on-Insulator Digital Circuits
- Experimental demonstration of tolerance to FWM crosstalk in wavelength-swept WDM access systems
- A PVT Tolerant STM-16 Clock-and-Data Recovery LSI Using an On-Chip Loop-Gain Variation Compensation Architecture in 0.20-μm CMOS-SOI
- Loss budget in single-fiber loopback access networks with ASE light source considering gain compression effect of GS-SOA
- An Injection-Controlled 10-Gb/s Burst-Mode CDR Circuit for a 1G/10G PON System
- Ultra Fast Response AC-Coupled Burst-Mode Receiver with High Sensitivity and Wide Dynamic Range for 10G-EPON System
- Area-Effective Inductive Peaking with Interwoven Inductor for High-Speed Laser-Diode Driver for Optical Communication System
- Body-Charge-Induced Switching Characteristics in Fully Depleted Silicon-on-Insulator Digital Circuits
- Small and Low-Cost Dual-Rate Optical Triplexer for OLT Transceivers in 10G/1G Co-existing 10G-EPON Systems
- Timestamp-based time and frequency synchronization over λ-tunable WDM/TDM-PON
- Multilevel transmission technique employing optical amplitude domain multiplexing
- Dynamic load-balancing by monitoring traffic volume for λ-tunable WDM/TDM-PON
- Dynamic wavelength allocation method consistent with DBA grant for λ-tunable WDM/TDM-PON