NOGAWA Masafumi | NTT Microsystem Integration Laboratories, NTT Corporation

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概要

• NOGAWA Masafumiの詳細を見る
• 同名の論文著者
• NTT Microsystem Integration Laboratories, NTT Corporationの論文著者

関連著者

• OHTOMO Yusuke

  NTT Microsystem Integration Laboratories, NTT Corporation

• NOGAWA Masafumi

  NTT Microsystem Integration Laboratories, NTT Corporation

• NISHIMURA Kazuyoshi

  NTT Microsystem Integration Laboratories, NTT Corporation

• KIMURA Shunji

  NTT Access Network Service Systems Laboratories, NTT Corporation

• YOSHIDA Tomoaki

  NTT Access Network Service Systems Laboratories, NTT Corporation

• KAWAMURA Tomoaki

  NTT Microsystem Integration Laboratories, NTT Corporation

• TOGASHI Minoru

  NTT Microsystem Integration Laboratories, NTT Corporation

• KUMOZAKI Kiyomi

  NTT Access Network Service Systems Laboratories, NTT Corporation

• Ohtomo Yusuke

  Ntt Microsystem Integration Laboratories Ntt Corporation

• Nogawa Masafumi

  Ntt Microsystem Integration Laboratories Ntt Corporation

• Nishimura Kazuyoshi

  Ntt Microsystem Integration Laboratories Ntt Corporation

• Nishimura Kazuyoshi

  Ntt Microsystem Integration Laboratories

• Ohtomo Yusuke

  Ntt Microsystem Integration Laboratories Ntt Corp.

• Kumozaki Kiyomi

  Ntt Corp. Chiba‐shi Jpn

• Kumozaki Kiyomi

  Ntt Access Network Service Systems Laboratories Ntt Corporation

• Kimura Shunji

  Ntt Access Network Service Systems Laboratories Ntt Corporation

• Togashi Minoru

  Ntt Microsystem Integration Laboratories Ntt Corporation

• Yoshida Tomoaki

  Ntt Access Network Service Systems Laboratories Ntt Corporation

• Kawamura Tomoaki

  Ntt Microsystem Integration Laboratories Ntt Corporation

• KOIZUMI Hiroshi

  NTT Microsystem Integration Laboratories, NTT Corporation

• Koizumi Hiroshi

  Ntt Microsystem Integration Laboratories Ntt Corporation

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著作論文

• A 10-Gb/s Burst-Mode Clock-and-Data Recovery IC with Frequency-Adjusting Dual Gated VCOs
• A 10-Gb/s Burst-Mode Clock-and-Data Recovery IC with Frequency-Adjusting Dual Gated VCOs
• A PVT Tolerant STM-16 Clock-and-Data Recovery LSI Using an On-Chip Loop-Gain Variation Compensation Architecture in 0.20-μm CMOS-SOI

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