3-Gb/s CMOS 1:4 MUX and DEMUX ICs
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概要
- 論文の詳細を見る
We have developed a design technique for static logic circuits. Using this technique, we designed 1/2 divider-type 1:4 demultiplexer (DEMUX) and 2:1 selector-type 4:1 multiplexer (MUX) circuits, each of which is a key component in high-speed data multiplexing and demultiplexing. These circuits consist of double rail flip-flops (DR F/F). These flip-flops have a smaller mean internal capacitance than single rail flip-flops, making them suitable for high-speed operation. The DR F/F has a symmetric structure, so the double rail toggle flip-flop can put out an exactly balanced CK/CKN signal, which boosts the speed of the data flip-flops. The double rail structure enables 30% faster operation but consumes only 17% more power (per GHz) than a single rail circuit. In addition, our 0.25-μm process technology provides a 70% higher frequency operation than 0.5-μm process technology. At the supply voltage of 2. 2 V, the DEMUX circuit and the MUX circuit operate at 4.55 GHz and 2.98 GHz, respectively. In addition, the 0.25-μm DEMUX circuit and the MUX circuit respectively consume 6.0 mW/GHz and 13.7 mW/GHz (@1.3 V), which are only 12% of the power consumed by 3.3-V 0.5-μm circuits. Because of its high-speed and low-power characteristics, our design technique will greatly contribute to the progress of large-scale high-speed telecommunication systems.
- 社団法人電子情報通信学会の論文
- 1995-12-25
著者
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Ohtomo Y
Ntt System Electronics Lab. Atsugi‐shi Jpn
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Ohtomo Yusuke
Ntt System Electronics Laboratories
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KADO Yuichi
NTT Microsystem Integration Laboratories, NTT Corporation
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Kado Yuichi
NTT LSI Laboratories
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Kado Yuichi
Ntt Microsystem Integration Laboratories
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Kado Yuichi
Ntt Microsystem Integration Laboratories Ntt Corporation
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Ino Masayuki
Ntt Electronics Corp.
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Ino Masayuki
Ntt Lsi Laboratories
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Yasuda S
Renesas Device Design Itami‐shi Japan
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OHTOMO Yusuke
NTT LSI Laboratories
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YASUDA Sadayuki
NTT LSI Laboratories
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TSUCHIYA Toshiaki
NTT LSI Laboratories
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Tsuchiya T
Ntt Corp. Musashino‐shi Jpn
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