Omura Y | Ntt Lsi Laboratories
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概要
関連著者
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Omura Y
Ntt Lsi Laboratories
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Omura Yasuhisa
Electronics Department Kansai University
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Omura Y
Electronics High-technology Research Center And Faculty Of Engineering Kansai University
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Omura Yasuhisa
High-technology Research Center And Faculty Of Engineering Kansai University
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Omura Yasuhisa
High-technology Research Center
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Nakakubo A
Electronics High-technology Research Center And Faculty Of Engineering Kansai University
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Nakakubo Atsushi
Electronics, High-Technology Research Center and Faculty of Engineering, Kansai University
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中辻 博
京都大学大学院工学研究科
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YANAGI Shin-ichiro
High-Technology Research Center and Faculty of Engineering, Kansai University
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Yanagi S
Kansai Univ.
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KADO Yuichi
NTT Microsystem Integration Laboratories, NTT Corporation
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Omura Yasuhisa
NTT LSI Laboratories
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Kuribayashi Hiroki
Corporate R&d Laboratories Pioneer Corporation
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Nakatsuji Hiroshi
Electronics High-technology Research Center And Faculty Of Engineering Kansai University
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Nakatsuji Hiroshi
Department Of Synthetic Chemistry And Biological Chemistry Faculty Of Engineering Kyoto University
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Suzuki M
Kddi Res. And Dev. Lab. Inc. Kamifukuoka‐shi Jpn
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Suzuki Masao
NTT LSI Laboratories
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Kado Yuichi
NTT LSI Laboratories
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Koike Keiichi
NTT LSI Laboratories
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Izumi Katsutoshi
NTT LSI Laboratories
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Kado Yuichi
Ntt Microsystem Integration Laboratories
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Kado Yuichi
Ntt Microsystem Integration Laboratories Ntt Corporation
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Koike K
Ntt Systems Electronics Lab. Atsugi‐shi Jpn
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Tamura Susumu
High-technology Research Center And Faculty Of Engineering Kansai University
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Nakahara Sumio
High-technology Research Center And Faculty Of Engineering Kansai University
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Omura Yasuhisa
Department Of Electronics Kansai University
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KOBAYASHI Hideki
High-Technology Research Center and Faculty of Engineering, Kansai University
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IIDA Yukio
High-Technology Research Center and Faculty of Engineering, Kansai University
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Iida Y
High-technology Research Center And Faculty Of Engineering Kansai University
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NAKAKUBO Atsushi
High-Technology Research Center and Faculty of Engineering, Kansai University
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Yanagi Shin-ichiro
High-technology Research Center
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Kobayashi H
Institute Of Scientific And Industrial Research Osaka University:crest Japan Science And Technology
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Nakatsuji Hiroshi
High-technology Research Center And Department Of Electronics Faculty Of Engineering Kansai Universi
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Komiya Kenji
Electronics Department Kansai University
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清水 明
Center For Atmospheric And Oceanic Studies Graduate School Of Science Tohoku University
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Nakamori Yasuhiko
Electronics Department, Kansai University
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Moriguchi Kohei
Electronics Department, Kansai University
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Moriguchi Kohei
Electronics Department Kansai University
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Nakamori Yasuhiko
Electronics Department Kansai University
著作論文
- A 1GHz/0.9mW CMOS/SIMOX Divide-by 128/129 Dual-Modulus Prescaler Using a Divide-by 2/3 Synchronous Counter
- An Experimental Full-CMOS Multigigahertz PLL LSI Using 0.4μm Gate Ultrathin-Film SIMOX Technology (Special Issue on Sub-Half Micron Si Device and Process Technologies)
- Single-Mode Silicon Optical Switch with T-Shaped SiO_2 Optical Waveguide as a Control Gate
- Study on Silicon Optical Switch with T-Shape SiO_2 Waveguide as an Optical Control Gate
- Quantum Mechanical Influence on Flat-Band Capacitance for Metal-Oxide-Semiconductor Structures with Nanometer-Thick Silicon Oxide Film and the Impact of Oxide Charge Evaluation
- Quantum mechanical effect in temperature dependence of threshold voltage of extremely thin SOI MOSFETs
- Quantization Effect in Temperature Dependence of Threshold Voltage of Extremely-Thin SOI MOSFETs
- Physics-based model of quantum-mechanical wave function penetration into thin dielectric films for evaluating modern MOS capacitors
- Effect of Silicon Addtion on Electrical Properties of SrBi2Ta2O9 Thin Films
- Effect of Silicon Addition on Electrical Properties of SrBi_2Ta_2O_9 Thin Films
- A Partial-Ground-Plane (PGP) Silicon-on-Insulator (SOI) Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) for Deep Sub-0.1μm Channel Regime
- Proposal of a Partial-Ground-Plane (PGP) Silicon-on-Insulator (SOI) MOSFET for Deep sub-0.1-μm Channel Regime
- Proposal of a Partial-Ground-Plane(PGP) Silicon-on-Insulator(SOI) MOSFET for Deep Sub-100-nm Channel Regime
- Physical and Mathematical Basis for the Crucial Technical Shortcoming of the Split C-V Technique in Thin-SOI MOSFET's