Koike K | Ntt Systems Electronics Lab. Atsugi‐shi Jpn
スポンサーリンク
概要
関連著者
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Koike K
Ntt Systems Electronics Lab. Atsugi‐shi Jpn
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KADO Yuichi
NTT Microsystem Integration Laboratories, NTT Corporation
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Omura Y
Electronics High-technology Research Center And Faculty Of Engineering Kansai University
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Omura Y
Ntt Lsi Laboratories
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Omura Yasuhisa
Electronics Department Kansai University
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Omura Yasuhisa
NTT LSI Laboratories
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Suzuki M
Kddi Res. And Dev. Lab. Inc. Kamifukuoka‐shi Jpn
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Suzuki Masao
NTT LSI Laboratories
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Kado Yuichi
NTT LSI Laboratories
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Koike Keiichi
NTT LSI Laboratories
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Izumi Katsutoshi
NTT LSI Laboratories
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Kado Yuichi
Ntt Microsystem Integration Laboratories
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Kado Yuichi
Ntt Microsystem Integration Laboratories Ntt Corporation
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Oguchi Satoshi
Semiconductor Amp Ic Division Hitachi Ltd.
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Hara H
Ntt Multimedia Networks Lab. Yokosuka‐shi Jpn
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Ono T
Nec Corp. Kawasaki‐shi Jpn
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Noto Takayuki
Semiconductor Amp Ic Division Hitachi Ltd.
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Nishio Yoji
Hitachi Research Laboratory, Hitachi, Ltd.
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Hara Hideo
Semiconductor amp IC Division, Hitachi, Ltd.
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Iwamura Masahiro
Hitachi Research Laboratory, Hitachi, Ltd.
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Kaminaga Yasuo
Hitachi Research Laboratory, Hitachi, Ltd.
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Koike Katsunori
Hitachi Engineering Company
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Hirose Kosaku
Semiconductor amp IC Division, Hitachi, Ltd.
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Yamamoto Yoshihiko
Semiconductor amp IC Division, Hitachi, Ltd.
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Ono Takeshi
Hitachi Microcomputer System Ltd.
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Nishio Y
Hitachi Ltd. Kokubunji‐shi Jpn
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Nishio Yoji
Hitachi Research Laboratory Hitachi Ltd.
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Hirose Kosaku
Semiconductor Amp Ic Division Hitachi Ltd.
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Kaminaga Yasuo
Hitachi Research Laboratory Hitachi Ltd.
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Hara Hideo
Semiconductor Amp Ic Division Hitachi Ltd.
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Iwamura M
Hitachi Ltd.
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Iwamura Masahiro
Hitachi Research Laboratory Hitachi Ltd.
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Yamamoto Yoshihiko
Semiconductor Amp Ic Division Hitachi Ltd.
著作論文
- A 1GHz/0.9mW CMOS/SIMOX Divide-by 128/129 Dual-Modulus Prescaler Using a Divide-by 2/3 Synchronous Counter
- An Experimental Full-CMOS Multigigahertz PLL LSI Using 0.4μm Gate Ultrathin-Film SIMOX Technology (Special Issue on Sub-Half Micron Si Device and Process Technologies)
- Design of the Basic Cell and Metallized RAM for 0.5μm CMOS Gate Array