Design of the Basic Cell and Metallized RAM for 0.5μm CMOS Gate Array
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概要
- 論文の詳細を見る
A 0.5μm CMOS embedded function type gate array family with high speed modules was developed. This family has : an effective basic cell ; high speed, compiled type metallized and diffused RAMs ; PLL (Phase Locked Loop) ; and GTL (Gunning Transceiver Logic) to realize operation of over 100 MHz at 3.3 V. This paper describes the basic cell architecture and the compiled type metallized RAM. A divided MOS transistor type basic cell is effective for metallized modules such as metallized RAM and internal logic circuits. The appropriate basic cell size (height) can be decided from the viewpoints of the relationship between the number of usable basic cells and the basic cell height, and the logic circuit speed. Propagation delay time of the 2-input NAND is 200 ps at a standard load of fan out=2 and metal length=1.4 mm. For the universal ASIC, the compiled RAM is indispensable. Single port and multi-port metallized RAMs which are structured by using the basic cells are discussed. The new single port memory cell circuit which has a differential write and single end read operating method is introduced. This memory cell circuit can be realized using one basic cell. The diffused layer region of the NMOS transfer gates for the read operation is shared between neighbor memory cells. So, the capacitance of the bit line becomes smaller, and a high speed access time can be achieved. The measured access time of 1 kbits is 4.2 ns. The new multi-port memory cell circuits which have a single end write and single end read operating method are introduced. The read operating method is the same as that of the single port memory cell circuit. The access time shows very high speed operation comparable to that of the single port memory. This 3F (Flexible, Fast, and Friendly) ASIC family can be applied to high speed processors in workstations and graphics equipment.
- 社団法人電子情報通信学会の論文
- 1995-09-25
著者
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Oguchi Satoshi
Semiconductor Amp Ic Division Hitachi Ltd.
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Hara H
Ntt Multimedia Networks Lab. Yokosuka‐shi Jpn
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Ono T
Nec Corp. Kawasaki‐shi Jpn
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Koike K
Ntt Systems Electronics Lab. Atsugi‐shi Jpn
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Noto Takayuki
Semiconductor Amp Ic Division Hitachi Ltd.
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Nishio Yoji
Hitachi Research Laboratory, Hitachi, Ltd.
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Hara Hideo
Semiconductor amp IC Division, Hitachi, Ltd.
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Iwamura Masahiro
Hitachi Research Laboratory, Hitachi, Ltd.
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Kaminaga Yasuo
Hitachi Research Laboratory, Hitachi, Ltd.
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Koike Katsunori
Hitachi Engineering Company
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Hirose Kosaku
Semiconductor amp IC Division, Hitachi, Ltd.
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Yamamoto Yoshihiko
Semiconductor amp IC Division, Hitachi, Ltd.
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Ono Takeshi
Hitachi Microcomputer System Ltd.
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Nishio Y
Hitachi Ltd. Kokubunji‐shi Jpn
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Nishio Yoji
Hitachi Research Laboratory Hitachi Ltd.
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Hirose Kosaku
Semiconductor Amp Ic Division Hitachi Ltd.
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Kaminaga Yasuo
Hitachi Research Laboratory Hitachi Ltd.
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Hara Hideo
Semiconductor Amp Ic Division Hitachi Ltd.
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Iwamura M
Hitachi Ltd.
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Iwamura Masahiro
Hitachi Research Laboratory Hitachi Ltd.
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Yamamoto Yoshihiko
Semiconductor Amp Ic Division Hitachi Ltd.
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