Fabrication and Characterization of 1 k-bit 1T2C-Type Ferroelectric Memory Cell Array
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概要
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A 1 k-bit 1T2C-type ferroelectric memory cell array has been designed and fabricated by combination of a 0.35 μm design rule for the complementary metal-oxide-semiconductor (CMOS) process and a 3 μm design rule for the ferroelectric and interconnection processes. Basic operations such as random access writing and readout operations, nondestructive data readout for more than $10^{4}$ readout pulses, data retention for 10 days, and data disturbance characteristics for more than $10^{4}$ unipolar pulses have been demonstrated in the fabricated 1T2C-type cell array.
- 2005-04-15
著者
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Kim Hyun-soo
Department Of Internal Medicine Chonnam National University Medical School
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Ishiwara Hiroshi
Department Of Applied Electronics Tokyo Institute Of Technology
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ISHIKAWA Toru
R&D Association for Future Electron Devices
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FUCHIKAMI Takaaki
R&D Association for Future Electron Devices
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OHKI Hiroshi
R&D Association for Future Electron Devices
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Fuchikami Takaaki
R&D Association for Future Electron Devices, 2-9-14 Toranomon, Minato-ku, Tokyo 105-0001, Japan
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Kim Hyun-Soo
Department of Advanced Applied Electronics, Interdisciplinary Graduate School of Science and Engineering, Tokyo Institute of Technology, 4259 Nagatsuta, Midori-ku, Yokohama 226-8502, Japan
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Ishiwara Hiroshi
Department of Advanced Applied Electronics, Interdisciplinary Graduate School of Science and Engineering, Tokyo Institute of Technology, 4259 Nagatsuta, Midori-ku, Yokohama 226-8502, Japan
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Ishikawa Toru
R&D Association for Future Electron Devices, 2-9-14 Toranomon, Minato-ku, Tokyo 105-0001, Japan
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Ohki Hiroshi
R&D Association for Future Electron Devices, 2-9-14 Toranomon, Minato-ku, Tokyo 105-0001, Japan
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