Sub-10 ps Logic Operations in Josephson Four-Junction Logic (4JL) Gates
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概要
- 論文の詳細を見る
Sub-10 ps logic delays have been obtained in a Josephson four junction logic (4JL) gate. An experimental circuit including a logic chain of ten 4JL gates whose minimum junction size is 2.5 μm square has been fabricated using a Pb-alloy integration technology. The shortest switching delay has been measured to be 7 ps/gate for the fanout of 1 with a power dissipation of 4 μW/gate.
- 社団法人応用物理学会の論文
- 1983-05-20
著者
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NAKAGAWA Hiroshi
Electrotechical Laboratory (ETL)
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Takada Susumu
Electrotechnical Laboratory
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Takada S
Saitama Univ. Urawa‐shi Jpn
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HAYAKAWA Hisao
Electrotechnical Laboratory
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Hayakawa H
Nagoya Univ. Nagoya Jpn
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Nakagawa Hiroshi
Graduate School Of Materials Science Nara Institute Of Science And Technology
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Odake Takeshi
Electrotechnical Laboratory:(present Address)scientific Computer Research Association
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Sogawa Eiichi
Electrotechnical Laboratory
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