Goto Satoshi | Waseda Univ. Jpn
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概要
関連著者
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Goto Satoshi
Waseda Univ. Jpn
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Goto Satoshi
Graduate School Of Information Production And System Waseda University
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GOTO Satoshi
Graduate School of Information, Production and Systems, Waseda University
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Goto Satoshi
Graduate School of Infomlation Production and Systems Waseda University
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Ikenaga Takeshi
Graduate School Of Information Production And System Waseda University
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Ikenaga Takeshi
Graduate School Of Ips Waseda University
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Ikenaga Takeshi
Ips Waseda University
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GOTO Satoshi
Waseda University
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Ikenaga Takeshi
Waseda Univ.
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Ishikawa Tatsuyuki
Graduate School Of Information Production And Systems Waseda University
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Ikenaga Takeshi
Graduate school of Information, Production and Systems, Waseda University
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IKENAGA Takeshi
Graduate School of Fundamental Science and Engineering, Waseda University
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IKENAGA Takeshi
IPS, Waseda University
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IKENAGA Takeshi
The Graduate School of Information, Production and Systems, Waseda University
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Zhou Dajiang
Waseda Univ. Kitakyushu‐shi Jpn
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Zhou Dajiang
Graduate School Of Information Production And Systems Waseda University
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Zhang Tianruo
Graduate School Of Information Production And System Waseda University
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Goto Satoshi
Waseda Univ.
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GOTO Satoshi
IPS, Waseda University
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Zhang Tianruo
Graduate school of Information, Production and Systems, Waseda University
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SONG Yang
Graduate School of Information, Production and Systems, Waseda University
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CHEN Zhixiang
Graduate School of Information, Production and Systems, Waseda University
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Peng Xiao
Waseda Univ. Kitakyushu‐shi Jpn
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Zhao Xiongxin
Waseda Univ. Kitakyushu‐shi Jpn
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Chen Zhixiang
Waseda Univ. Kitakyushu‐shi Jpn
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Song Yang
Graduate School Of Ips Waseda University
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Zhao Xiongxin
Graduate School Of Information Production And Systems Waseda University
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Chen Zhixiang
Graduate School Of Information Production And Systems Waseda University
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Peng Xiao
Graduate School Of Information Production And Systems Waseda University
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Xiongxin Zhao
School of Information, Production and Systems, Waseda University
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HUANG Yiqing
IPS, Waseda University
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Liu Qin
Nanjing Univ.
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Huang Yiqing
Graduate School Of Information Production And System Waseda University
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SHIMIZU Kazunori
IPS, Waseda University
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Zhu Jiayi
Department Of Electronic Engineering Shanghai Jiao Tong University
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Zhou Jinjia
Graduate School Of Information Production And Systems Waseda University
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Tian Guifen
Graduate School Of Information Production And System Waseda University
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Shimizu Kazunori
Ips Waseda University
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PENG Xiao
Graduate School of Information, Production and Systems, Waseda University
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ZHAO Xiongxin
Graduate School of Information, Production and Systems, Waseda University
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You Wenqi
Graduate School Of Ips Waseda University
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Goto Satoshi
Graduate School Of Information Production And Systems Waseda University
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DONG Sheqin
EDA lab, Department of Computer Science and Technology, Tsinghua University
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Goto Satoshi
Ips Waseda University
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Song Yang
Graduate School Of Information Production And Systems Waseda University
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Liu Chen
Graduate School Of Information Production And System Waseda University
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Dong Sheqin
Eda Lab Department Of Computer Science And Technology Tsinghua University
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Wang Minghui
Graduate School Of Information Production And System Waseda University
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LIU Qin
IPS, Waseda University
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Shimizu Kazunori
Graduate School Of Information Production And Systems Waseda University
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IKENAGA Takeshi
Waseda University
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ZHAO Kang
EDA lab, Department of Computer Science and Technology, Tsinghua University
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BIAN Jinian
EDA lab, Department of Computer Science and Technology, Tsinghua University
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TOGAWA Nozomu
Dept. of Computer Science, Waseda University
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Wei Xianghui
Graduate School of Information, Production and Systems, Waseda University
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Togawa Nozomu
Dept. Of Computer Science Waseda University
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Jin Xin
Graduate School Of Information Production And System Waseda University
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Wei Xianghui
Graduate School Of Information Production And Systems Waseda University
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Tian Guifen
Graduate school of Information, Production and Systems, Waseda University
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You Wenqi
Graduate School of Information, Production and Systems LSI, Waseda University
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Wang Jun
Graduate School Of Ips Waseda University
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LIU Chen
Graduate School of Information, Production and System, Waseda University
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ZHOU Jinjia
Graduate School of Information, Production and Systems, Waseda University
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Bian Jinian
Eda Lab Department Of Computer Science And Technology Tsinghua University
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Zhao Kang
Eda Lab Department Of Computer Science And Technology Tsinghua University
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Zhao Kang
Eda Lab Dep. Of Computer Sci. And Technol. Tsinghua Univ.
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Bian Jinian
Eda Lab Dep. Of Computer Sci. And Technol. Tsinghua Univ.
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Togawa Nozomu
Dept. of Computer Science and Engineering, Waseda University
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MAEHARA Fumiaki
Department of Science and Engineering, Waseda University
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WANG Lei
University of Electro-Communications
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Tian Guifen
Waseda Univ.
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Ikenaga Takeshi
Department of Information, Production and Systems, Waseda University
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Goto Satoshi
Department of Information, Production and Systems, Waseda University
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ISHIKAWA Tatsuyuki
Graduate School of Information, Production and Systems, Waseda University
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Ho Hsing-Ying
Graduate School of Information, Production and Systems, Waseda University
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WANG Minghui
Graduate School of Information, Production and System, Waseda University
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JIN Xin
Graduate School of Information, Production and System, Waseda University
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Liu Zhenyu
Kitakyushu Foundation For The Advancement Of Industry Science And Technology
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Togawa N
Univ. Kitakyushu Kitakyushu‐shi Jpn
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Togawa Nozomu
The Dept. Of Computer Science Waseda University
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Yanagisawa Masao
Department Of Computer Science Waseda University
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Abe Yuta
Graduate School Of Information Production And Systems Waseda University
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Liu Zhenyu
Ips Waseda University
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Yanagisawa Masao
Waseda University
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Zhou Dajiang
Ips Waseda University
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ZHU Jiayi
Department of Electronic Engineering, Shanghai Jiao Tong University
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FAN Yibo
IPS, Waseda University
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Wang Lei
Ips Waseda University
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Fan Yibo
Ips Waseda University
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Maehara Fumiaki
Waseda Univ. Tokyo Jpn
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Maehara Fumiaki
Department Of Radiology School Of Medicine Fukuoka University
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Maehara Fumiaki
Department Of Science And Engineering Waseda University
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Ikenaga Takeshi
Department Of Computer Science And Electronics Kyushu Institute Of Technology
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Goto Satoshi
Department Of Civil And Environmental Engineering University Of Yamanashi
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Chen Song
Graduate School Of Ips Waseda University
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Chen Song
Graduate School Of Information Production And Systems Waseda University
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Ho Hsing-ying
Graduate School Of Information Production And Systems Waseda University
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JI Wen
Graduate School of Information, Production and Systems, Waseda University
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Ji Wen
Graduate School Of Information Production And Systems Waseda University
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HE Xun
Graduate School of Information, Production and Systems, Waseda University
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Yu Bei
Eda Lab Department Of Computer Science And Technology Tsinghua University
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He Xun
Graduate School Of Information Production And Systems Waseda University
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Liu Zhenyu
Tsinghua University
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Jin Xin
Information Technology Research Organization Waseda University
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Togawa Nozomu
Waseda University
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Togawa Nozomu
Waseda Univ.
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SODE TANAKA
Renesas Electronics Corp.
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HE Gang
Graduate School of Information, Production and Systems, Waseda University
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He Gang
Graduate School Of Information Production And Systems Waseda University
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Wang Jun
Graduate School Of Engineering Yokohama National University
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Goto Satoshi
The Graduate School Of Information Production And Systems Waseda University
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Chen Song
The Graduate School Of Information Production And Systems Waseda University
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Masao Yanagisawa
School of Fundamental Science and Engineering Waseda University
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JIN Xin
Graduate School at Shenzhen, Tsinghua University, and IT Research Organization, Waseda Univ.
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Goto Satoshi
Department of Chemistry, Faculty of Science and Technology, Sophia University
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Wang Qi
Graduate School Of Information Production And Systems Waseda University
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Tian Guifen
Department of Information, Production and Systems, Waseda University
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Zhang Tianruo
Department of Information, Production and Systems, Waseda University
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YOU Wenqi
Waseda University
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SONG Yang
Waseda University
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TOGAWA Nozomu
Department of Computer Science, Waseda University
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YOU Wenqi
Department of Information, Production and Systems, Waseda University
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WEI Xianghui
Department of Information, Production and Systems, Waseda University
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SONG Yang
Department of Information, Production and Systems, Waseda University
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Ma Yao
Graduate school of IPS, Waseda University
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Zhuan Yang
Graduate school of IPS, Waseda University
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Song Yang
Department Of Electronic Engineering Shanghai Jiao Tong University
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LIU Qin
Graduate School of Information, Production, and Systems, WASEDA University
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HUANG Yiqing
The Graduate School of Information, Production and Systems, Waseda University
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SONG Yang
IPS, Waseda University
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GOTO Satoshi
the Graduate School of Information, Production and Systems, Waseda University
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Huang Yiqing
Waseda Univ. Kitakyushu‐shi Jpn
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SHIMIZU Kazunori
Dept. of Computer Science, Waseda University
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HIRATSUKA Seiichiro
IPS, Waseda University
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USHIKI Shinsuke
IPS, Waseda University
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WANG Lei
Graduate School of Information, Production, and Systems, Waseda University
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WANG Lei
IPS, Waseda University
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WANG Jun
IPS, Waseda University
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Song Yang
Waseda Univ. Kitakyushu‐shi Jpn
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CHEN Song
Graduate School of Natural Science and Technology, Okayama University
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CHEN Xianmin
Department of Electronic Engineering, Shanghai Jiao Tong University
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LIU Peilin
Department of Electronic Engineering, Shanghai Jiao Tong University
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ZHOU Dajiang
IPS, Waseda University
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PAN Xingguang
Department of Electronic Engineering, Shanghai Jiao Tong University
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ZHANG Tianruo
Waseda University
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Ushiki Shinsuke
Ips Waseda University
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Hiratsuka Seiichiro
Ips Waseda University
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Ma Yao
Graduate School Of Ips Waseda University
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Liu Peilin
Department Of Electronic Engineering Shanghai Jiao Tong University
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Zhuan Yang
Graduate School Of Ips Waseda University
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Chen Xianmin
Department Of Electronic Engineering Shanghai Jiao Tong University
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Pan Xingguang
Department Of Electronic Engineering Shanghai Jiao Tong University
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CHEN Zhenxing
Graduate School of Information, Production and Systems, Waseda University
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Yoshimura T
Ntt Docomo Inc. Yokohama‐shi Jpn
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Chen Zhenxing
Graduate School Of Information Production And Systems Waseda University
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LIU Qin
Waseda University
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LIU Zhenyu
Graduate School of Information, Production and Systems, Waseda University
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LIU Zhenyu
IPS, Waseda University
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Yoshimura Takeshi
The Graduate School Of Information Production And System Waseda University
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JI Wen
Waseda University
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ABE Yuta
Waseda University
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YU Bei
EDA lab, Department of Computer Science and Technology, Tsinghua University
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Togawa Nozomu
Department Of Computer Science And Engineering Waseda University
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Chen Song
The Graduate School Of Information Production And System Waseda University
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Wang Lei
Graduate School Of Information Systems The University Of Eletro-communications
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Zhang Tianruo
Graduate School Of Information Production And Systems Waseda University
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Okamura Leona
Graduate School Of Information Production And System Waseda University
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Ikenaga Takeshi
The Graduate School Of Information Production And Systems Waseda University
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Zhong Wei
The Graduate School Of Information Production And Systems Waseda University
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Yu Bei
The Department Of Electrical And Computer Engineering The University Of Texas At Austin
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Dong Sheqin
The Department Of Computer Science & Technology Tsinghua University
著作論文
- BS-12-19 A Fast Block Type Decision Algorithm for H.264/AVC Intra Prediction(BS-12. Network Planning, Control, and Management)
- D-11-50 A Novel Fast Block Type Decision Algorithm for Intra Prediction in H.264/AVC High Profile
- D-11-14 A Mode Reduction Based Fast Integer Motion Estimation Algorithm for HDTV
- A-16-2 A Fast Mode Decision Algorithm for H.264/AVC Intra Prediction
- A LOW-POWER AND PERFORMANCE-AWARE DVB-S2 LDPC DECODER WITH LAYERED SCHEDULING
- Region-of-Interest based Preprocessing for H.264/AVC Encoding
- A Macroblock Homogeneity Detection Method and its Application for Block Size Decision in H.264/AVC
- Fast Inter Mode Decision Algorithm Based on Residual Feature
- Pipeline-Based Partition Exploration for Heterogeneous Multiprocessor Synthesis
- Efficient Fully-Parallel LDPC Decoder Design with Improved Simplified Min-Sum Algorithms(VLSI Architecture for Communication/Server Systems,VLSI Technology toward Frontiers of New Market)
- Power-Efficient LDPC Decoder Architecture Based on Accelerated Message-Passing Schedule(VLSI Architecture,VLSI Design and CAD Algorithms)
- Partially-Parallel LDPC Decoder Achieving High-Efficiency Message-Passing Schedule(Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
- Reconfigurable Adaptive FEC System Based on Reed-Solomon Code with Interleaving(Adaptive Signal Processing, Recent Advances in Circuits and Systems-Part 1)
- BS-12-18 A Novel Hardware-Friendly Regular 3-Step Integer Motion Estimation Algorithm for H.264/AVC(BS-12. Network Planning, Control, and Management)
- A-16-11 Level C+ Bandwidth Reduction Method for MPEG-2 to H.264 Transcoding
- A-16-1 Group-Based Prediction Scheme on Multiple Reference Frame Fractional Motion Estimation in H.264/AVC
- D-11-70 Adaptive Spatial EC based on Numerical Measures of Edge Statistical Model
- A-4-15 Cross Low Pass Filter Based Subsampling Algorithm for H.264/AVC Motion Estimation
- BS-12-20 VLSI Design of Level C Bandwidth Reduction Scheme for MPEG-2 to H.264/AVC Transcoding(BS-12. Network Planning, Control, and Management)
- Low Power LDPC Code Decoder Architecture Based on Intermediate Message Compression Technique
- A 41mW VGA【triple bond】fps Quadtree Video Encoder for Video Surveillance Systems
- Standard Deviation and Intra Prediction Mode Based Adaptive Spatial Error Concealment (SEC) in H.264/AVC
- Variable Block Size Motion Vector Retrieval Schemes for H.264 Inter Frame Error Concealment
- A high-parallelism reconfigurable permutation network for IEEE 802.11n/803.16e LDPC decoder (情報理論)
- Pipeline-Based Partition Exploration for Heterogeneous Multiprocessor Synthesis
- Exploring Partitions Based on Search Space Smoothing for Heterogeneous Multiprocessor System
- Fast Custom Instruction Identification Algorithm Based on Basic Convex Pattern Model for Supporting ASIP Automated Design
- Permutation Network for Reconfigurable LDPC Decoder Based on Banyan Network
- Implementation of LDPC decoder for 802.16e (情報理論)
- An multi-rate LDPC decoder system on FPGA (情報理論)
- An Efficient Motion Vector Coding Scheme Based on Prioritized Reference Decision
- A High Performance and Low Bandwidth Multi-Standard Motion Compensation Design for HD Video Decoder
- A 48 Cycles/MB H.264/AVC Deblocking Filter Architecture for Ultra High Definition Applications
- A High-Speed Design of Montgomery Multiplier
- Reconfigurable Variable Block Size Motion Estimation Architecture for Search Range Reduction Algorithm
- D-11-17 MOTION CORRELATION ADAPTION BASED INTER MODE DECISION ALGORITHM FOR H.264/AVC
- High Throughput VLSI Architecture of a Fast Mode Decision Algorithm for H.264/AVC Intra Encoding
- Adaptive Sub-Sampling Based Reconfigurable SAD Tree Architecture for HDTV Application
- Hardware-Oriented Early Detection Algorithms for 4×4 and 8×8 All-Zero Blocks in H.264
- VLSI Oriented Fast Motion Estimation Algorithm Based on Pixel Difference, Block Overlapping and Motion Feature Analysis
- Adaptive Search Range Algorithms for Variable Block Size Motion Estimation in H.264/AVC
- Content-Aware Fast Motion Estimation for H.264/AVC
- Edge Block Detection and Motion Vector Information Based Fast VBSME Algorithm
- Parallel Improved HDTV720p Targeted Propagate Partial SAD Architecture for Variable Block Size Motion Estimation in H.264/AVC
- A-4-18 Integer Search Position Based Fast Motion Estimation in H.264/AVC
- A High Performance Partially-Parallel Irregular LDPC Decoder Based on Sum-Delta Message Passing Schedule
- A-4-33 High Throughput Rate-1/2 Partially-Parallel Irregular LDPC Decoder
- A Bandwidth Optimized, 64 Cycles/MB Joint Parameter Decoder Architecture for Ultra High Definition H.264/AVC Applications
- An Ultra-Low Bandwidth Design Method for MPEG-2 to H.264/AVC Transcoding
- Voltage and Level-Shifter Assignment Driven Floorplanning
- A-6-12 Prediction-based Center-bias Fast Fractional Motion Estimation Algorithm for H.264/AVC
- Generic Permutation Network for QC-LDPC Decoder
- ROI based Computational Complexity Reduction Scheme for H.264/AVC Encoder
- Multiple Region-of-Interest Based H.264 Encoder with a Detection Architecture in Macroblock Level Pipelining
- A 530Mpixels/s Intra Prediction Architecture for Ultra High Definition H.264/AVC Encoder
- Greedy Optimization Algorithm for the Power/Ground Network Design to Satisfy the Voltage Drop Constraint
- Cache Based Motion Compensation Architecture for Quad-HD H.264/AVC Video Decoder
- A 115mW 1Gbps QC-LDPC Decoder ASIC for WiMAX in 65nm CMOS
- A 98GMACs/W 32-Core Vector Processor in 65nm CMOS
- A 6.72-Gb/s 8 pJ/bit/iteration IEEE 802.15.3c LDPC Decoder Chip
- Greedy Algorithm for the On-Chip Decoupling Capacitance Optimization to Satisfy the Voltage Drop Constraint
- Cluster Generation and Network Component Insertion for Topology Synthesis of Application-Specific Network-on-Chips