Togawa Nozomu | Department Of Computer Science And Engineering Waseda University

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概要

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著作論文

A Fast Selector-Based Subtract-Multiplication Unit and Its Application to Butterfly Unit
Power-Efficient LDPC Decoder Architecture Based on Accelerated Message-Passing Schedule(VLSI Architecture,VLSI Design and CAD Algorithms)
Floorplan-Aware High-Level Synthesis for Generalized Distributed-Register Architectures
A Circuit Partitioning Algorithm with Path Delay Constraints for Multi-FPGA Systems (Special Section of Selected Papers from the 9th Karuizawa Workshop on Circuits and Systems)
A Simultaneous Technology Mapping, Placement, and Global Routing Algorithm for FPGAs with Path Delay Constraints (Special Section of Selected Papers from the 8th Karuizawa Workshop on Circuits and Systems)
A Circuit Partitioning Algorithm with Replication Capability for Multi-FPGA Systems
Selective Low-Care Coding : A Means for Test Data Compression in Circuits with Multiple Scan Chains(Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
A SIMD Instruction Set and Functional Unit Synthesis Algorithm with SIMD Operation Decomposition(Programmable Logic, VLSI, CAD and Layout, Recent Advances in Circuits and Systems-Part 1)
Sub-operation Parallelism Optimization in SIMD Processor Core Synthesis(Selected Papers from the 17th Workshop on Circuits and Systems in Karuizawa)
A Hardware/Software Cosynthesis Algorithm for Processors with Heterogeneous Datapaths(Selected Papers from the 16th Workshop on Circuits and Systems in Karuizawa)
A Hardware/Software Partitioning Algorithm for Processor Cores with Packed SIMD-Type Instructions(Design Methodology)(VLSI Design and CAD Algorithms)
A Retargetable Simulator Generator for DSP Processor Cores with Packed SIMD-type Instructions(Simulation Acceletor)(VLSI Design and CAD Algorithms)
A Retargetable Simulator Generator for DSP Processor Cores with Packed SIMD-type Instructions
A Hardware/Software Cosynthesis System for Processor Cores with Content Addressable Memories
A High-Level Energy-Optimizing Algorithm for System VLSIs Based on Area/Time/Power Estimation(Special Section on VLSI Design and CAD Algorithms)
An Algorithm and a Flexible Architecture for Fast Block-Matching Motion Estimation(Special Section on VLSI Design and CAD Algorithms)
High-Level Area/Delay/Power Estimation for Low Power System VLSIs with Gated Clocks(Special Section of Selected Papers from the 14th Workshop on Circuits and Systems in Karuizawa)
An Area/Time Optimizing Algorithm in High-Level Synthesis of Control-Based Hardwares (Special Section on Discrete Mathematics and Its Applications)
A Two-Level Cache Design Space Exploration System for Embedded Applications
An L1 Cache Design Space Exploration System for Embedded Applications
A Scan-Based Attack Based on Discriminators for AES Cryptosystems
Unified Dual-Radix Architecture for Scalable Montgomery Multiplications in GF(P) and GF(2^n)
Scan-Based Side-Channel Attack against RSA Cryptosystems Using Scan Signatures
A Hardware/Software Cosynthesis System for Digital Signal Processor Cores (Special Section on VLSI Design and CAD Algorithms)
A Depth-Constrained Technology Mapping Algorithm for Logic-Blocks Composed of Tree-Structured LUTs (Special Section on Selected Papers from the 11th Workshop on Circuits and Systems in Karuizawa)
A Locality-Aware Hybrid NoC Configuration Algorithm Utilizing the Communication Volume among IP Cores
Exact, Fast and Flexible L1 Cache Configuration Simulation for Embedded Systems
Energy-efficient High-level Synthesis for HDR Architectures
A Fast Weighted Adder by Reducing Partial Product for Reconstruction in Super-Resolution
Energy-efficient High-level Synthesis for HDR Architectures with Clock Gating Based on Concurrency-oriented Scheduling
A Thermal-Aware High-Level Synthesis Algorithm for RDR Architectures through Binding and Allocation
Floorplan Driven Architecture and High-Level Synthesis Algorithm for Dynamic Multiple Supply Voltages
Energy-efficient High-level Synthesis for HDR Architectures with Clock Gating Based on Concurrency-oriented Scheduling
A Delay-variation-aware High-level Synthesis Algorithm for RDR Architectures

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