KIMURA Shinji | Graduate School of Information Science, Nara Institute of Science and Technology

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概要

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著作論文

Exact Minimization of Free BDDs and Its Application to Pass-Transistor Logic Optimization (Special Section on VLSI Design and CAD Algorithms)
Hardware Synthesis from C Programs with Estimation of Bit Length of Variables (Special Section on VLSI Design and CAD Algorithms)
Selective Low-Care Coding : A Means for Test Data Compression in Circuits with Multiple Scan Chains(Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
The Optimal Architecture Design of Two-Dimension Matrix Multiplication Jumping Systolic Array
Fine-Grained Power Gating Based on the Controlling Value of Logic Elements
Fine-grained power gating based on the controlling value of logic gates (VLSI設計技術)
Fine-grained power gating based on the controlling value of logic gates (システムLSI設計技術)
Issue Mechanism for Embedded Simultaneous Multithreading Processor
Bit Length Optimization of Fractional Part on Floating to Fixed Point Conversion for High-Level Synthesis(Logic and High Synthesis)(VLSI Design and CAD Algorithms)
RAY-SPACE CODING USING SINUSOIDAL STRUCTURE IN CIRCULAR CAMERA ARRANGEMENT(International Workshop on Advanced Image Technology 2006)
Bit-Length Optimization Method for High-Level Synthesis Based on Non-linear Programming Technique(System Level Design,VLSI Design and CAD Algorithms)
A Selective Scan Chain Reconfiguration through Run-Length Coding for Test Data Compression and Scan Power Reduction(Test)(VLSI Design and CAD Algorithms)
A Hybrid Dictionary Test Data Compression for Multiscan-Based Designs(Test)(VLSI Design and CAD Algorithms)
Optimizing Controlling-Value-Based Power Gating with Gate Count and Switching Activity

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