Watanabe K | Graduate School Of Information Science Nara Institute Of Science And Technology

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概要

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著作論文

Exact Minimization of Free BDDs and Its Application to Pass-Transistor Logic Optimization (Special Section on VLSI Design and CAD Algorithms)
Hardware Synthesis from C Programs with Estimation of Bit Length of Variables (Special Section on VLSI Design and CAD Algorithms)
Timing Verification of Sequential Logic Circuits Based on Controlled Multi-Clock Path Analysis (Special Section on VLSI Design and CAD Algorithms)
A Scheduling Problem in Multihop Networks
The p-Collection Problem in a Flow Network with Lower Bounds (Special Section on Discrete Mathematics and Its Applications)
Covering Problems in the p-Collection Problems
The Problem of where to Locate p-Sinks in a Flow Network: Complexity Approach
Realization Problems of a Tree with a Transmission Number Sequence (Special Section on the 6th Karuizawa Workshop on Circuits and Systems)
Multi-Cycle Path Detection Based on Propositional Satisfiability with CNF Simplification Using Adaptive Variable Insertion (Special Section on VLSI Design and CAD Algorithms)
Bit Length Optimization of Fractional Part on Floating to Fixed Point Conversion for High-Level Synthesis(Logic and High Synthesis)(VLSI Design and CAD Algorithms)
A CMOS Rail-to-Rail Current Conveyer and Its Applications to Current-Mode Filters(Special Section on Papers Selected from ITC-CSCC 2002)
A CMOS Rail-to-Rail Current Conveyor
Look Up Table Compaction Based on Folding of Logic Functions(Special Section on VLSI Design and CAD Algorithms)
Class A CMOS Current Conveyors
A Clock-Feedthrough Compensated Switched-Current Memory Cell
Automatic Generation of Java-Based, Database-Independent Query API
Automatic Generation of Java-Based, Database-Independent Query API

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