Look Up Table Compaction Based on Folding of Logic Functions(Special Section on VLSI Design and CAD Algorithms)
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概要
- 論文の詳細を見る
The paper describes the folding method of logic functions to reduce the size of memories to keep the functions. The folding is based on the relation of fractions of logic functions. If the logic function includes 2 or 3 same parts, then only one part should be kept and other parts can be omitted. We show that the logic function of 1-bit addition can be reduced to half size using the bit-wise NOT relation and the bit-wise OR relation. The paper also introduces 3-1 LUT's with the folding mechanism. A full adder can be implemented using only one 3-1 LUT with the folding. Multi-bit AND and OR operations can be mapped to our LUT's not using the extra cascading circuit but using the carry circuit for addition. We have also tested the mapping capability of 4 input functions to our 3-1 LUT's with folding and carry propagation mechanisms. We have shown the reduction of the area consumption when using our LUT's compared to the case using 4-1 LUT's on several benchmark circuits.
- 社団法人電子情報通信学会の論文
- 2002-12-01
著者
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堀山 貴史
埼玉大学情報システム工学科
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Kimura Shinji
Waseda Univ. Kitakyushu‐shi Jpn
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Kimura Shinji
Graduate School Of Information Production And Systems Waseda University
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Kimura S
Waseda Univ. Kitakyushu‐shi Jpn
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WATANABE Kaoru
The author is with Osaka Electro-Communication University
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Watanabe Katsumasa
Nara Institute Of Technology
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Ishii Atsushi
Nara Institute Of Science And Technology:(present Address)the Nomura Research Institute Ltd.
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Watanabe K
Graduate School Of Information Science Nara Institute Of Science And Technology
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HORIYAMA Takashi
Nara Institute of Science and Technology
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NAKANISHI Masaki
Nara Institute of Science and Technology
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KAJIHARA Hirotsugu
Nara Institute of Science and Technology
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Nakanishi Masaki
The Graduate School Of Information Science Nara Institute Of Science And Technology
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Nakanishi Masaki
Nara Inst. Sci. And Technol. Ikoma‐shi Jpn
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Kohara Shunitsu
Department Of Computer Science Waseda University
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NAKANISHI Masaki
Yamagata University
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Watanabe Katsumasa
Nara Institute of Science and Technology
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