Timing Verification of Sequential Logic Circuits Based on Controlled Multi-Clock Path Analysis (Special Section on VLSI Design and CAD Algorithms)
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概要
- 論文の詳細を見る
This paper introduces a new kind of false path, which is sensitizable but does not affect the decision of the maximum clock frequency. Such false paths exist in multi-clock operations controlled by waiting states, and the delay time of these paths can be greater than the clock period. This paper proposes a method to detect these waiting false paths based on the symbolic state traversal. In this method, the maximum allowable clock cycle of each path is computed using update cycles of each register.
- 社団法人電子情報通信学会の論文
- 1998-12-25
著者
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Takagi K
Nagoya Univ. Nagoya‐shi Jpn
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NAKAMURA Kazuhiro
the Graduate School of Information Science, Nara Institute of Science and Technology
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KIMURA Shinji
the Graduate School of Information Science, Nara Institute of Science and Technology
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TAKAGI Kazuyoshi
the Graduate School of Information Science, Nara Institute of Science and Technology
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WATANABE Katsumasa
the Graduate School of Information Science, Nara Institute of Science and Technology
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Kimura Shinji
Graduate School Of Information Production And Systems Waseda University
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Kimura S
Waseda Univ. Kitakyushu‐shi Jpn
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WATANABE Kaoru
The author is with Osaka Electro-Communication University
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Watanabe Katsumasa
The Graduate School Of Information Science Nara Institute Of Science And Technology
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Nakamura Kazuhiro
The Graduate School Of Information Science Nara Institute Of Science And Technology
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Watanabe K
Graduate School Of Information Science Nara Institute Of Science And Technology
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Nakamura K
Takasago Research & Development Center Mitsubishi Heavy Industries Ltd.
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Kohara Shunitsu
Department Of Computer Science Waseda University
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Kimura Shinji
The Graduate School Of Information Science Advanced Institute Of Science And Technology
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Nakamura Kazuhiro
The Graduate School Of Information Science Nagoya University
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TAKAGI Kazuyoshi
the Graduate School of Informatics, Kyoto University
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