Ohtsuki T | Waseda Univ. Tokyo Jpn

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概要

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著作論文

FPGA-Based Reconfigurable Adaptive FEC(System Level Design)(VLSI Design and CAD Algorithms)
Floorplan-Aware High-Level Synthesis for Generalized Distributed-Register Architectures
Selective Low-Care Coding : A Means for Test Data Compression in Circuits with Multiple Scan Chains(Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
A Fast Elliptic Curve Cryptosystem LSI Embedding Word-Based Montgomery Multiplier (System LSIs and Microprocessors, VLSI Design Technology in the Sub-100nm Era)
A SIMD Instruction Set and Functional Unit Synthesis Algorithm with SIMD Operation Decomposition(Programmable Logic, VLSI, CAD and Layout, Recent Advances in Circuits and Systems-Part 1)
Sub-operation Parallelism Optimization in SIMD Processor Core Synthesis(Selected Papers from the 17th Workshop on Circuits and Systems in Karuizawa)
High-Level Power Optimization Based on Thread Partitioning(System Level Design)(VLSI Design and CAD Algorithms)
A Hardware/Software Cosynthesis Algorithm for Processors with Heterogeneous Datapaths(Selected Papers from the 16th Workshop on Circuits and Systems in Karuizawa)
A Hardware/Software Partitioning Algorithm for Processor Cores with Packed SIMD-Type Instructions(Design Methodology)(VLSI Design and CAD Algorithms)
A Retargetable Simulator Generator for DSP Processor Cores with Packed SIMD-type Instructions(Simulation Acceletor)(VLSI Design and CAD Algorithms)
A Two-Level Cache Design Space Exploration System for Embedded Applications
An L1 Cache Design Space Exploration System for Embedded Applications
A Selective Scan Chain Reconfiguration through Run-Length Coding for Test Data Compression and Scan Power Reduction(Test)(VLSI Design and CAD Algorithms)
A Hybrid Dictionary Test Data Compression for Multiscan-Based Designs(Test)(VLSI Design and CAD Algorithms)
A Scan-Based Attack Based on Discriminators for AES Cryptosystems
X-Handling for Current X-Tolerant Compactors with More Unknowns and Maximal Compaction
Unified Dual-Radix Architecture for Scalable Montgomery Multiplications in GF(P) and GF(2^n)
A Unified Test Compression Technique for Scan Stimulus and Unknown Masking Data with No Test Loss
A Secure Test Technique for Pipelined Advanced Encryption Standard
Scan-Based Side-Channel Attack against RSA Cryptosystems Using Scan Signatures

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