Ohtsuki Tatsuo | Department Of Computer Science And Engineering Waseda University

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概要

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著作論文

A Fast Selector-Based Subtract-Multiplication Unit and Its Application to Butterfly Unit
FPGA-Based Reconfigurable Adaptive FEC(System Level Design)(VLSI Design and CAD Algorithms)
Floorplan-Aware High-Level Synthesis for Generalized Distributed-Register Architectures
Fast Scheduling and Allocation Algorithms for Entropy CODEC (Special Issue on Synthesis and Verification of Hardware Design)
A Circuit Partitioning Algorithm with Path Delay Constraints for Multi-FPGA Systems (Special Section of Selected Papers from the 9th Karuizawa Workshop on Circuits and Systems)
A Simultaneous Technology Mapping, Placement, and Global Routing Algorithm for FPGAs with Path Delay Constraints (Special Section of Selected Papers from the 8th Karuizawa Workshop on Circuits and Systems)
A Circuit Partitioning Algorithm with Replication Capability for Multi-FPGA Systems
Selective Low-Care Coding : A Means for Test Data Compression in Circuits with Multiple Scan Chains(Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
A Fast Elliptic Curve Cryptosystem LSI Embedding Word-Based Montgomery Multiplier (System LSIs and Microprocessors, VLSI Design Technology in the Sub-100nm Era)
A SIMD Instruction Set and Functional Unit Synthesis Algorithm with SIMD Operation Decomposition(Programmable Logic, VLSI, CAD and Layout, Recent Advances in Circuits and Systems-Part 1)
Sub-operation Parallelism Optimization in SIMD Processor Core Synthesis(Selected Papers from the 17th Workshop on Circuits and Systems in Karuizawa)
High-Level Power Optimization Based on Thread Partitioning(System Level Design)(VLSI Design and CAD Algorithms)
A Hardware/Software Cosynthesis Algorithm for Processors with Heterogeneous Datapaths(Selected Papers from the 16th Workshop on Circuits and Systems in Karuizawa)
A Hardware/Software Partitioning Algorithm for Processor Cores with Packed SIMD-Type Instructions(Design Methodology)(VLSI Design and CAD Algorithms)
A Retargetable Simulator Generator for DSP Processor Cores with Packed SIMD-type Instructions(Simulation Acceletor)(VLSI Design and CAD Algorithms)
A Retargetable Simulator Generator for DSP Processor Cores with Packed SIMD-type Instructions
A Hardware/Software Cosynthesis System for Processor Cores with Content Addressable Memories
A High-Level Energy-Optimizing Algorithm for System VLSIs Based on Area/Time/Power Estimation(Special Section on VLSI Design and CAD Algorithms)
An Algorithm and a Flexible Architecture for Fast Block-Matching Motion Estimation(Special Section on VLSI Design and CAD Algorithms)
C-5 A Software/Hardware Codesign for MPEG Encoder
High-Level Area/Delay/Power Estimation for Low Power System VLSIs with Gated Clocks(Special Section of Selected Papers from the 14th Workshop on Circuits and Systems in Karuizawa)
A New Hardware/Software Partitioning Algorithm for DSP Processor Cores with Two Types of Register Files(Special Section on VLSI Design and CAD Algorithms)
Area and Delay Estimation in Hardware/Software Cosynthesis for Digital Signal Processor Cores(Special Section on VLSI Design and CAD Algorithms)
An Area/Time Optimizing Algorithm in High-Level Synthesis of Control-Based Hardwares (Special Section on Discrete Mathematics and Its Applications)
CAM Processor Synthesis Based on Behavioral Descriptions (Special Section on VLSI Design and CAD Algorithms)
A Hardware / Software Cosynthesis System for Digital Signal Processor Cores with Two Types of Register Files (Special Section of Selected Papers from the 12th Workshop on Circuit and Systems in Karuizawa)
Direct-Detection Optical Synchronous CDMA Systems with Interference Canceller Using Group Information Codes (Special Section on Spread Spectrum Techniques and Applications)
Optical Spread Time CDMA Communication Systems with PPM Signaling
Performance Analysis of Optical Frequency-Domain Encoding CDMA Enhancement of Frequency Division Multiplexing
A Two-Level Cache Design Space Exploration System for Embedded Applications
An L1 Cache Design Space Exploration System for Embedded Applications
A Built-in Reseeding Technique for LFSR-Based Test Pattern Generation(Timing Verification and Test Generation)(VLSI Design and CAD Algorithms)
A Built-in Reseeding Technique for LFSR-Based Test Pattern Generation
A Selective Scan Chain Reconfiguration through Run-Length Coding for Test Data Compression and Scan Power Reduction(Test)(VLSI Design and CAD Algorithms)
A Hybrid Dictionary Test Data Compression for Multiscan-Based Designs(Test)(VLSI Design and CAD Algorithms)
A CAM-Based Parallel Fault Simulation Algorithm with Minimal Storage Size
A Scan-Based Attack Based on Discriminators for AES Cryptosystems
X-Handling for Current X-Tolerant Compactors with More Unknowns and Maximal Compaction
Unified Dual-Radix Architecture for Scalable Montgomery Multiplications in GF(P) and GF(2^n)
A Unified Test Compression Technique for Scan Stimulus and Unknown Masking Data with No Test Loss
A Secure Test Technique for Pipelined Advanced Encryption Standard
Scan-Based Side-Channel Attack against RSA Cryptosystems Using Scan Signatures
A Hardware/Software Cosynthesis System for Digital Signal Processor Cores (Special Section on VLSI Design and CAD Algorithms)
A Depth-Constrained Technology Mapping Algorithm for Logic-Blocks Composed of Tree-Structured LUTs (Special Section on Selected Papers from the 11th Workshop on Circuits and Systems in Karuizawa)
A Fast Scheduling Algorithm Based on Gradual Time-Frame Reduction for Datapath Synthesis
An FPGA Layout Reconfiguration Algorithm Based on Global Routes for Engineering Changes in System Design Specifications(Special Section on Discrete Mathematics and Its Applications)
Exact, Fast and Flexible L1 Cache Configuration Simulation for Embedded Systems

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