Direct-Detection Optical Synchronous CDMA Systems with Interference Canceller Using Group Information Codes (Special Section on Spread Spectrum Techniques and Applications)
スポンサーリンク
概要
- 論文の詳細を見る
We propose a new interference cancellation technique using reference signals for optical synchronous code-division multiple-access (CDMA) systems. In the proposed system, we use the signature code sequences composed of the group information codes and the modified prime code sequences. The group information codes are added in the forefront of the signature code sequences to estimate the amount of the multiple access interference (MAi). The proposed cancellation scheme can be realized with the simpler structure than the conventional canceller using the time division reference signal, because it can reduce the number of optical correlators from P to two where P is the prime number. We analyze the performance of the proposed system with considering the effects of the MAI, avalanche photodiode (APD) noise, and thermal noise. We show that the proposed canceller has better bit error probability than the conventional canceller.
- 社団法人電子情報通信学会の論文
- 2000-11-25
著者
-
Sasase I
Keio Univ. Yokohama‐shi Jpn
-
Sasase Iwao
The Department Of Information And Computer Science Keio University
-
Sasase Iwao
The Faculty Of Science And Technology Keio University
-
Ohtsuki Tatsuo
Department Of Computer Science And Engineering Waseda University
-
OHTSUKI Tomoaki
the Department of Information and Computer Scinece, Keio University
-
Ohtsuki Tomoaki
The Department Of Electrical Engineering Science University Of Tokyo
-
Ohtsuki Tomoaki
Department Of Electrical Engineering Tokyo University Of Science
-
SAWAGASHIRA Hiroshi
the Department of Information and Computer Science, Keio University
-
KAMAKURA Katsuhiro
the Department of Information and Computer Science, Keio University
-
Ohtsuki Tomoaki
The Faculty Of Science And Technology Science University Of Tokyo
-
Ohtsuki T
Department Of Electrical Engineering Tokyo University Of Science
-
Kamakura K
Keio Univ. Yokohama‐shi Jpn
-
Kamakura Katsuhiro
The Department Of Information And Computer Science Keio University
-
Sasase Iwao
The Department Of Electrical Engineering Faculty Of Science And Technology Keio University
-
Sawagashira Hiroshi
The Department Of Information And Computer Science Keio University
-
OHTSUKI Tomoaki
the Department of Computer and Information Science, Keio University
関連論文
- Spreading Code Assignment for Multicarrier CDMA System over Frequency-Selective Fading Channels(Terrestrial Radio Communications)
- Inter-Code Interference and Optimum Spreading Sequence in Frequency-Selective Rayleigh Fading Channels on Uplink MC-CDMA(Signal Processing for Communications)(Digital Signal Processing)
- A Fast Selector-Based Subtract-Multiplication Unit and Its Application to Butterfly Unit
- FPGA-Based Reconfigurable Adaptive FEC(System Level Design)(VLSI Design and CAD Algorithms)
- Floorplan-Aware High-Level Synthesis for Generalized Distributed-Register Architectures
- Fast Scheduling and Allocation Algorithms for Entropy CODEC (Special Issue on Synthesis and Verification of Hardware Design)
- A Performance-Oriented Simultaneous Placement and Global Routing Algorithm for Transport-Processing FPGAs (Special Section on VLSI Design and CAD Algorithms)
- A Circuit Partitioning Algorithm with Path Delay Constraints for Multi-FPGA Systems (Special Section of Selected Papers from the 9th Karuizawa Workshop on Circuits and Systems)
- Simultaneous Placement and Global Routing for Transport-Processing FPGA Layout (Special Section on VLSI Design and CAD Algorithms)
- A Simultaneous Technology Mapping, Placement, and Global Routing Algorithm for FPGAs with Path Delay Constraints (Special Section of Selected Papers from the 8th Karuizawa Workshop on Circuits and Systems)
- A Circuit Partitioning Algorithm with Replication Capability for Multi-FPGA Systems
- Maple : A Simultaneous Technology Mapping, Placement, and Global Routing Algorithm for Field-Programmable Gate Arrays (Special Section on VLSI Design and CAD Algorithms)
- Selective Low-Care Coding : A Means for Test Data Compression in Circuits with Multiple Scan Chains(Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
- A Fast Elliptic Curve Cryptosystem LSI Embedding Word-Based Montgomery Multiplier (System LSIs and Microprocessors, VLSI Design Technology in the Sub-100nm Era)
- A SIMD Instruction Set and Functional Unit Synthesis Algorithm with SIMD Operation Decomposition(Programmable Logic, VLSI, CAD and Layout, Recent Advances in Circuits and Systems-Part 1)
- Sub-operation Parallelism Optimization in SIMD Processor Core Synthesis(Selected Papers from the 17th Workshop on Circuits and Systems in Karuizawa)
- High-Level Power Optimization Based on Thread Partitioning(System Level Design)(VLSI Design and CAD Algorithms)
- A Hardware/Software Cosynthesis Algorithm for Processors with Heterogeneous Datapaths(Selected Papers from the 16th Workshop on Circuits and Systems in Karuizawa)
- A Hardware/Software Partitioning Algorithm for Processor Cores with Packed SIMD-Type Instructions(Design Methodology)(VLSI Design and CAD Algorithms)
- A Retargetable Simulator Generator for DSP Processor Cores with Packed SIMD-type Instructions(Simulation Acceletor)(VLSI Design and CAD Algorithms)
- A Retargetable Simulator Generator for DSP Processor Cores with Packed SIMD-type Instructions
- A Hardware/Software Cosynthesis System for Processor Cores with Content Addressable Memories
- A High-Level Energy-Optimizing Algorithm for System VLSIs Based on Area/Time/Power Estimation(Special Section on VLSI Design and CAD Algorithms)
- An Algorithm and a Flexible Architecture for Fast Block-Matching Motion Estimation(Special Section on VLSI Design and CAD Algorithms)
- C-5 A Software/Hardware Codesign for MPEG Encoder
- High-Level Area/Delay/Power Estimation for Low Power System VLSIs with Gated Clocks(Special Section of Selected Papers from the 14th Workshop on Circuits and Systems in Karuizawa)
- A New Hardware/Software Partitioning Algorithm for DSP Processor Cores with Two Types of Register Files(Special Section on VLSI Design and CAD Algorithms)
- Area and Delay Estimation in Hardware/Software Cosynthesis for Digital Signal Processor Cores(Special Section on VLSI Design and CAD Algorithms)
- An Area/Time Optimizing Algorithm in High-Level Synthesis of Control-Based Hardwares (Special Section on Discrete Mathematics and Its Applications)
- CAM Processor Synthesis Based on Behavioral Descriptions (Special Section on VLSI Design and CAD Algorithms)
- A Hardware / Software Cosynthesis System for Digital Signal Processor Cores with Two Types of Register Files (Special Section of Selected Papers from the 12th Workshop on Circuit and Systems in Karuizawa)
- Multiple Subcarrier Modulation for Infrared Wireless Systems Using Punctured Convolutional Codes and Variable Amplitude Block Codes(Optical Wireless Communications)
- Equalization for Infrared Wireless Systems Using OOK-CDMA
- Indoor Infrared Wireless Systems Using OOK-CDMA with Decision-Feedback Equalizer on Diffuse Channels
- A New Viterbi Algorithm with Adaptive Path Reduction Method (Special Section on Information Theory and Its Applications)
- Trellis Coded Modulation Using Totally Overlapped Signal Sets
- Cutoff Rate Analysis of Overlapping Multi-Pulse Pulse Position Modulation (OMPPM) in Optical Direct-Detection Channel (Special Section on Information Theory and Its Applications)
- Access Timing Controlled Direct-Detection Optical CDMA Systems with PPM Signaling (Special Section on Information Theory and Its Applications)
- Effects of Hard-Limiter and Error Correction Coding on Performance of Direct-Detection Optical CDMA Systems with PPM Signaling
- Coding for Multi-Pulse PPM with Imperfect Slot Synchronization in Optical Direct-Detection Channels
- Lower Bounds on Capacity and Cutoff Rate of Differential Overlapping Pulse Position Modulation in Optical Direct-Detection Channel
- Error Performance of Overlapping Multi-Pulse Pulse Position Modulation (OMPPM) and Trellis Coded OMPPM in Optical Direct-Detection Channel
- Performance Analysis of Multi-Pulse PPM with Imperfect Slot Synchronization in Optical Direct-Detection Channel
- Performance Analysis of Multi-Pulse Pulse Position Modulation (MPPM) in Noisy Photon Counting Channel (Special Section on Information Theory and Its Applications)
- Capacity and Cutoff Rate of Overlapping Multi-Pulse Pulse Position Modulation (OMPPM) in Optical Direct-Detection Channel: Quantum-Limited Case (Special Section on Information Theory and Its Applications)
- The Effects of Laser Phase Noise on Optical Coherent Coded Subcarrier Multiplexing System with Distributing Local Oscillator in Local Loop (Special Issue on Optical/Microwave Interaction Devices, Circuits and Systems)
- Coherent Optical Polarization-Shift-Keying (POLSK) Homodyne System Using Phase-Diversity Receivers
- Parallel Rate-Variable Punctured Convolutional Coded PPM in Photon Communicaiton
- Trellis Coded Modulation using Partially Overlapped Signal Sets of Non-equiprobable Signaling (Special Issue on Personal Communications)
- Direct-Detection Optical Synchronous CDMA Systems with Interference Canceller Using Group Information Codes (Special Section on Spread Spectrum Techniques and Applications)
- Optical Spread Time CDMA Communication Systems with PPM Signaling
- Performance Analysis of Optical Frequency-Domain Encoding CDMA Enhancement of Frequency Division Multiplexing
- Performance Analysis of Optical Synchronous PPM/CDMA Systems with Interference Canceller Under Number-State Light Field (Special Issue on Optical Access Networks toward Life Enhancement)
- Performance Analysis of Coherent Optical POLSK Receivers with Local Oscillator Intensity Noise and Unmatched Quantum Efficiencies
- The Mitigation of MAI for OOK-CDMA Systems with Optical Hard-Limiters by Transmitting Optical Pulses with Two-Level Intensities(Fiber-Optic Transmission)
- The Mitigation of MAI for OOK-CDMA Systems with Optical Hard-Limiters by Transmitting Optical Pulses with Two-Level Intensities
- A Two-Level Cache Design Space Exploration System for Embedded Applications
- An L1 Cache Design Space Exploration System for Embedded Applications
- Information and Signal Processing for Sensor Networks(Wide Band Systems)
- A Built-in Reseeding Technique for LFSR-Based Test Pattern Generation(Timing Verification and Test Generation)(VLSI Design and CAD Algorithms)
- A Built-in Reseeding Technique for LFSR-Based Test Pattern Generation
- Low-Density Parity-Check (LDPC) Coded OFDM Systems : Bit Error Rate and the Number of Decoding Iterations(Wireless Communication Technology)
- A Selective Scan Chain Reconfiguration through Run-Length Coding for Test Data Compression and Scan Power Reduction(Test)(VLSI Design and CAD Algorithms)
- A Hybrid Dictionary Test Data Compression for Multiscan-Based Designs(Test)(VLSI Design and CAD Algorithms)
- Multiple Pre-Rake Filtering Based on the Predicted Channel Impulse Response in the Transmitter and a Rake Combiner in the Receiver for TDD/DS-CDMA Mobile Communication Systems
- A CAM-Based Parallel Fault Simulation Algorithm with Minimal Storage Size
- A Scan-Based Attack Based on Discriminators for AES Cryptosystems
- X-Handling for Current X-Tolerant Compactors with More Unknowns and Maximal Compaction
- Unified Dual-Radix Architecture for Scalable Montgomery Multiplications in GF(P) and GF(2^n)
- A Unified Test Compression Technique for Scan Stimulus and Unknown Masking Data with No Test Loss
- A Secure Test Technique for Pipelined Advanced Encryption Standard
- Scan-Based Side-Channel Attack against RSA Cryptosystems Using Scan Signatures
- RP-Reconstruncting ARP Strategy for Micro-Cellular Systems
- A Fast Viterbi Decoding in Optical Channels
- A Hardware/Software Cosynthesis System for Digital Signal Processor Cores (Special Section on VLSI Design and CAD Algorithms)
- A Depth-Constrained Technology Mapping Algorithm for Logic-Blocks Composed of Tree-Structured LUTs (Special Section on Selected Papers from the 11th Workshop on Circuits and Systems in Karuizawa)
- A Fast Scheduling Algorithm Based on Gradual Time-Frame Reduction for Datapath Synthesis
- An FPGA Layout Reconfiguration Algorithm Based on Global Routes for Engineering Changes in System Design Specifications(Special Section on Discrete Mathematics and Its Applications)
- Computational Complexity Reduction of MLD Based on SINR in MIMO Spatial Multiplexing Systems (Antennas and Propagation)
- Performance of Restricted Connective Semi-Random Network
- Trellis Coded 8PSK Modulation with Diversity on Spatially Correlated Rayleigh Fading Channel
- Performance Analysis of Multi-Pulse Pulse Position Modulation Using Avalanche Photodiode in Optical Intersatellite Links
- Input and Output Queueing Nonblocking Switch with Feed-Back Loop
- Coherence Multiplexed/Subcarrier Multiplexing (CM/SCM) Lightwave System For Microcelluler Mobile Communications
- Bandwidth Division Type Parallel Combinatory DS-CDMA System(Special Section on Information Theory and Its Applications)
- Double-Stage Threshold-Type Foreground-Background Congestion Control for Common-Store Queueing System with Multiple Nonpreemptive Priority Classes
- Traffic Analysis of Multimedia Queueing System with Poisson and Batch Poisson Packet Arrivals
- Multibits/Sequence-Period Optical CDMA Receiver with Double Optical Hardlimiters(Spread Spectrum Technologies and Applications)
- Direct-Detection Optical Synchronous CDMA Systems with Channel Interference Canceller Using Time Division Reference Signal (Special Section on Spread Spectrum Techniques and Applications)
- Exact, Fast and Flexible L1 Cache Configuration Simulation for Embedded Systems
- Input and Output Queueing Two Stage ATM Switch with Hot-Spot Route
- State Classification with Array Sensor Using Support Vector Machine for Wireless Monitoring Systems