A CAM-Based Parallel Fault Simulation Algorithm with Minimal Storage Size
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概要
- 論文の詳細を見る
CAMs (Content Addressable Memories) are functional memories which have functions such as word-parallel equivalence search, bilateral 1-bit data shifting between consecutive words, and word-parallel writing. Since CAMs can be integrated because of their regular structure, massively parallel CAM functions can be executed. Taking advantage of CAMs, Ishiura and Yajima have proposed a parallel fault simulation algorithm using a CAM. This algorithm, however, requires a large amount of CAM storage to simulate large-scale circuits. In this paper, we propose a new massively parallel fault simulation algorithm requiring less CAM storage, and compare it with Ishiura and Yajima's algorithm. Experimental results of the algorithm on CHARGE II-the CAM-based hardware engine developed in our laboratory-are also reported.
- 社団法人電子情報通信学会の論文
- 1995-12-25
著者
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Ohtsuki Tatsuo
Department of Computer Science and Engineering, Waseda University
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Sato Masao
Department Of Legal Medicine Fukushima Medical University School Of Medicine
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Ohtsuki Tatsuo
Department Of Computer Science And Engineering Waseda University
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Ohtsuki Tatsuo
Department Of Electronics And Communication Engineering Waseda University
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Ohno Shinsuke
Department of Electronics and Communication Engineering, Waseda University
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Ohno Shinsuke
Department Of Applied Chemistry Aichi Institute Of Technology
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Ohno Shinsuke
Department Of Electronics And Communication Engineering Waseda University
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Sato Masao
Department Of Applied Biological Chemistry Graduate School Of Bioresource And Bioenvironmental Scien
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Sato Masao
Department Of Electronics And Communication Engineering Waseda University
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