CAM Processor Synthesis Based on Behavioral Descriptions (Special Section on VLSI Design and CAD Algorithms)

スポンサーリンク

概要

• 論文の詳細を見る

• CAM(Content Addressable Memory) units are generally designed so that they can be applied to variety of application programs. However, if a particular application runs on CAM units, some functions in CAM units may be often used and other functions may never be used. We consider that appropriate design for CAM units is required depending on the requirements for a given application program. This paper proposes a CAM processor synthesis system based on behavioral descriptions. The input of the system is an application program written in C including CAM functions, and its output is hardware descriptions of a synthesized processor and a binary code executed on it. Since the system determines functions in CAM units and synthesizes a CAM processor depending on the requirements of an application program, we expect that a synthesized CAM processor can execute the application program with small processor area and delay. Experimental results demonstrate its efficiency and effectiveness.

• 社団法人電子情報通信学会の論文
• 2000-12-25

著者

• Togawa N

  Univ. Kitakyushu Kitakyushu‐shi Jpn

• Togawa Nozomu

  The Dept. Of Computer Science Waseda University

• OHTSUKI Tatsuo

  the Department of Electronics, Information and Communication Engineering, Waseda University

• Yanagisawa M

  The Dept. Of Computer Science Waseda University

• Yanagisawa Masao

  Department Of Computer Science Waseda University

• YANAGISAWA Masao

  the Department of Electronics, Information and Communication Engineering, Waseda University

• WAKUI Tatsuhiko

  Department of Electronics, Information and Communication Engineering, Waseda University

• TOGAWA Nozomu

  Advanced Research Institute for Science and Engineering, Waseda University

• WAKUI Tatsuhiko

  the Department of Electronics, Information and Communication Engineering, Waseda University

• YODEN Tatsuhiko

  the Department of Electronics, Information and Communication Engineering, Waseda University

• TERAJIMA Makoto

  the Department of Electronics, Information and Communication Engineering, Waseda University

• Ohtsuki Tatsuo

  Department Of Computer Science And Engineering Waseda University

• Ohtsuki Tatsuo

  The Department Of Electronics And Communication Engineering School Of Science And Engineering Waseda

• Yanagisawa Masao

  The Department Of Electronics Information And Communication Engineering Waseda University

• Ohtsuki Tomoaki

  The Department Of Electrical Engineering Science University Of Tokyo

• Wakui Tatsuhiko

  Department Of Electronics Information And Communication Engineering Waseda University

• Yoden Tatsuhiko

  The Department Of Electronics Information And Communication Engineering Waseda University

• Ohtsuki T

  Department Of Electrical Engineering Tokyo University Of Science

• Terajima Makoto

  The Department Of Electronics Information And Communication Engineering Waseda University:(present A

• Masao Yanagisawa

  School of Fundamental Science and Engineering Waseda University

• YANAGISAWA Masao

  the Department of Electronic and Photonic Systems, Waseda University

関連論文

• A Fast Selector-Based Subtract-Multiplication Unit and Its Application to Butterfly Unit
• FPGA-Based Reconfigurable Adaptive FEC(System Level Design)(VLSI Design and CAD Algorithms)
• Floorplan-Aware High-Level Synthesis for Generalized Distributed-Register Architectures
• Fast Scheduling and Allocation Algorithms for Entropy CODEC (Special Issue on Synthesis and Verification of Hardware Design)
• A Performance-Oriented Simultaneous Placement and Global Routing Algorithm for Transport-Processing FPGAs (Special Section on VLSI Design and CAD Algorithms)
• A Circuit Partitioning Algorithm with Path Delay Constraints for Multi-FPGA Systems (Special Section of Selected Papers from the 9th Karuizawa Workshop on Circuits and Systems)
• Simultaneous Placement and Global Routing for Transport-Processing FPGA Layout (Special Section on VLSI Design and CAD Algorithms)
• A Simultaneous Technology Mapping, Placement, and Global Routing Algorithm for FPGAs with Path Delay Constraints (Special Section of Selected Papers from the 8th Karuizawa Workshop on Circuits and Systems)
• A Circuit Partitioning Algorithm with Replication Capability for Multi-FPGA Systems
• Maple : A Simultaneous Technology Mapping, Placement, and Global Routing Algorithm for Field-Programmable Gate Arrays (Special Section on VLSI Design and CAD Algorithms)
• A High-Level Synthesis System for Digital Signal Processing Based on Data-Flow Graph Enumeration (Special Section on VLSI Design and CAD Algorithms)
• Selective Low-Care Coding : A Means for Test Data Compression in Circuits with Multiple Scan Chains(Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
• A Fast Elliptic Curve Cryptosystem LSI Embedding Word-Based Montgomery Multiplier (System LSIs and Microprocessors, VLSI Design Technology in the Sub-100nm Era)
• A SIMD Instruction Set and Functional Unit Synthesis Algorithm with SIMD Operation Decomposition(Programmable Logic, VLSI, CAD and Layout, Recent Advances in Circuits and Systems-Part 1)
• Sub-operation Parallelism Optimization in SIMD Processor Core Synthesis(Selected Papers from the 17th Workshop on Circuits and Systems in Karuizawa)
• High-Level Power Optimization Based on Thread Partitioning(System Level Design)(VLSI Design and CAD Algorithms)
• A Hardware/Software Cosynthesis Algorithm for Processors with Heterogeneous Datapaths(Selected Papers from the 16th Workshop on Circuits and Systems in Karuizawa)
• A Hardware/Software Partitioning Algorithm for Processor Cores with Packed SIMD-Type Instructions(Design Methodology)(VLSI Design and CAD Algorithms)
• A Retargetable Simulator Generator for DSP Processor Cores with Packed SIMD-type Instructions(Simulation Acceletor)(VLSI Design and CAD Algorithms)
• A Retargetable Simulator Generator for DSP Processor Cores with Packed SIMD-type Instructions
• A Hardware/Software Cosynthesis System for Processor Cores with Content Addressable Memories
• A High-Level Energy-Optimizing Algorithm for System VLSIs Based on Area/Time/Power Estimation(Special Section on VLSI Design and CAD Algorithms)
• An Algorithm and a Flexible Architecture for Fast Block-Matching Motion Estimation(Special Section on VLSI Design and CAD Algorithms)
• C-5 A Software/Hardware Codesign for MPEG Encoder
• High-Level Area/Delay/Power Estimation for Low Power System VLSIs with Gated Clocks(Special Section of Selected Papers from the 14th Workshop on Circuits and Systems in Karuizawa)
• A New Hardware/Software Partitioning Algorithm for DSP Processor Cores with Two Types of Register Files(Special Section on VLSI Design and CAD Algorithms)
• Area and Delay Estimation in Hardware/Software Cosynthesis for Digital Signal Processor Cores(Special Section on VLSI Design and CAD Algorithms)
• An Area/Time Optimizing Algorithm in High-Level Synthesis of Control-Based Hardwares (Special Section on Discrete Mathematics and Its Applications)
• CAM Processor Synthesis Based on Behavioral Descriptions (Special Section on VLSI Design and CAD Algorithms)
• A Hardware / Software Cosynthesis System for Digital Signal Processor Cores with Two Types of Register Files (Special Section of Selected Papers from the 12th Workshop on Circuit and Systems in Karuizawa)
• Multiple Subcarrier Modulation for Infrared Wireless Systems Using Punctured Convolutional Codes and Variable Amplitude Block Codes(Optical Wireless Communications)
• Equalization for Infrared Wireless Systems Using OOK-CDMA
• Indoor Infrared Wireless Systems Using OOK-CDMA with Decision-Feedback Equalizer on Diffuse Channels
• Cutoff Rate Analysis of Overlapping Multi-Pulse Pulse Position Modulation (OMPPM) in Optical Direct-Detection Channel (Special Section on Information Theory and Its Applications)
• Access Timing Controlled Direct-Detection Optical CDMA Systems with PPM Signaling (Special Section on Information Theory and Its Applications)
• Effects of Hard-Limiter and Error Correction Coding on Performance of Direct-Detection Optical CDMA Systems with PPM Signaling
• Coding for Multi-Pulse PPM with Imperfect Slot Synchronization in Optical Direct-Detection Channels
• Lower Bounds on Capacity and Cutoff Rate of Differential Overlapping Pulse Position Modulation in Optical Direct-Detection Channel
• Error Performance of Overlapping Multi-Pulse Pulse Position Modulation (OMPPM) and Trellis Coded OMPPM in Optical Direct-Detection Channel
• Performance Analysis of Multi-Pulse PPM with Imperfect Slot Synchronization in Optical Direct-Detection Channel
• Performance Analysis of Multi-Pulse Pulse Position Modulation (MPPM) in Noisy Photon Counting Channel (Special Section on Information Theory and Its Applications)
• Capacity and Cutoff Rate of Overlapping Multi-Pulse Pulse Position Modulation (OMPPM) in Optical Direct-Detection Channel: Quantum-Limited Case (Special Section on Information Theory and Its Applications)
• The Effects of Laser Phase Noise on Optical Coherent Coded Subcarrier Multiplexing System with Distributing Local Oscillator in Local Loop (Special Issue on Optical/Microwave Interaction Devices, Circuits and Systems)
• Coherent Optical Polarization-Shift-Keying (POLSK) Homodyne System Using Phase-Diversity Receivers
• Parallel Rate-Variable Punctured Convolutional Coded PPM in Photon Communicaiton
• Direct-Detection Optical Synchronous CDMA Systems with Interference Canceller Using Group Information Codes (Special Section on Spread Spectrum Techniques and Applications)
• Optical Spread Time CDMA Communication Systems with PPM Signaling
• Performance Analysis of Optical Frequency-Domain Encoding CDMA Enhancement of Frequency Division Multiplexing
• Performance Analysis of Optical Synchronous PPM/CDMA Systems with Interference Canceller Under Number-State Light Field (Special Issue on Optical Access Networks toward Life Enhancement)
• Performance Analysis of Coherent Optical POLSK Receivers with Local Oscillator Intensity Noise and Unmatched Quantum Efficiencies
• A Two-Level Cache Design Space Exploration System for Embedded Applications
• An L1 Cache Design Space Exploration System for Embedded Applications
• A Built-in Reseeding Technique for LFSR-Based Test Pattern Generation(Timing Verification and Test Generation)(VLSI Design and CAD Algorithms)
• A Built-in Reseeding Technique for LFSR-Based Test Pattern Generation
• Optimal Constraint Graph Generation Algorithm for Layout Compaction Using Enhanced Plane-Sweep Method (Special Section on Discrete Mathematics and Its Applications)
• A Selective Scan Chain Reconfiguration through Run-Length Coding for Test Data Compression and Scan Power Reduction(Test)(VLSI Design and CAD Algorithms)
• A Hybrid Dictionary Test Data Compression for Multiscan-Based Designs(Test)(VLSI Design and CAD Algorithms)
• A CAM-Based Parallel Fault Simulation Algorithm with Minimal Storage Size
• A Scan-Based Attack Based on Discriminators for AES Cryptosystems
• X-Handling for Current X-Tolerant Compactors with More Unknowns and Maximal Compaction
• Unified Dual-Radix Architecture for Scalable Montgomery Multiplications in GF(P) and GF(2^n)
• A Unified Test Compression Technique for Scan Stimulus and Unknown Masking Data with No Test Loss
• A Secure Test Technique for Pipelined Advanced Encryption Standard
• Scan-Based Side-Channel Attack against RSA Cryptosystems Using Scan Signatures
• A Hardware/Software Cosynthesis System for Digital Signal Processor Cores (Special Section on VLSI Design and CAD Algorithms)
• A Depth-Constrained Technology Mapping Algorithm for Logic-Blocks Composed of Tree-Structured LUTs (Special Section on Selected Papers from the 11th Workshop on Circuits and Systems in Karuizawa)
• A Fast Scheduling Algorithm Based on Gradual Time-Frame Reduction for Datapath Synthesis
• An FPGA Layout Reconfiguration Algorithm Based on Global Routes for Engineering Changes in System Design Specifications(Special Section on Discrete Mathematics and Its Applications)
• Computational Complexity Reduction of MLD Based on SINR in MIMO Spatial Multiplexing Systems (Antennas and Propagation)
• Performance Analysis of Multi-Pulse Pulse Position Modulation Using Avalanche Photodiode in Optical Intersatellite Links
• Greedy Optimization Algorithm for the Power/Ground Network Design to Satisfy the Voltage Drop Constraint
• Integrating Wearable Sensor Technology into Project-management Process
• Multibits/Sequence-Period Optical CDMA Receiver with Double Optical Hardlimiters(Spread Spectrum Technologies and Applications)
• Greedy Algorithm for the On-Chip Decoupling Capacitance Optimization to Satisfy the Voltage Drop Constraint
• Exact, Fast and Flexible L1 Cache Configuration Simulation for Embedded Systems
• Scan-based Attack against DES and Triple DES Cryptosystems Using Scan Signatures (Preprint)
• Energy-efficient High-level Synthesis for HDR Architectures
• Scan Vulnerability in Elliptic Curve Cryptosystems
• A Fault-Secure High-Level Synthesis Algorithm for RDR Architectures
• A Fast Selector-Based Subtract-Multiplication Unit and Its Application to Butterfly Unit
• Floorplan-Driven High-Level Synthesis for Distributed/Shared-Register Architectures
• A Fast Weighted Adder by Reducing Partial Product for Reconstruction in Super-Resolution
• Exact, Fast and Flexible L1 Cache Configuration Simulation for Embedded Systems
• A Locality-Aware Hybrid NoC Configuration Algorithm Utilizing the Communication Volume among IP Cores

もっと見る 閉じる

スポンサーリンク