Maple : A Simultaneous Technology Mapping, Placement, and Global Routing Algorithm for Field-Programmable Gate Arrays (Special Section on VLSI Design and CAD Algorithms)

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概要

• 論文の詳細を見る

• Technology mapping algorithms for LUT(Look Up Table) based FPGAs have been proposed to transfer a Boolean network into logic-blocks. However, since those algorithms take no layout information into account, they do not always lead to excellent results. In this paper, a simultaneous technology mapping, placement and global routing algorithm for FPGAs, Maple, is presented. Maple is an extended version of a simultaneous placement and global routing algorithm for FPGAs, which is based on recursive partition of layout regions and block sets. Maple inherits its basic process and executes the technology mapping simultaneously in each recursive process. Therefore, the mapping can be done with the placement and global routing information. Experimental results for some benchmark circuits demonstrate its efficiency and effectiveness.

• 社団法人電子情報通信学会の論文
• 1994-12-25

著者

• Sato M

  The Department Of Electronics Information And Communication Engineering Waseda University

• Togawa N

  Univ. Kitakyushu Kitakyushu‐shi Jpn

• Togawa Nozomu

  School of Science and Engineering, Waseda University

• Sato Masao

  School of Science and Engineering, Waseda University

• Ohtsuki Tatsuo

  School of Science and Engineering, Waseda University

• Ohtsuki Tatsuo

  School Of Science And Engineering Waseda University

• Ohtsuki T

  Department Of Electrical Engineering Tokyo University Of Science

• Ohtsuki Tatsuo

  School of Fundamental Science and Engineering, Waseda University

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