Floorplan-Driven High-Level Synthesis for Distributed/Shared-Register Architectures

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概要

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• In this paper, we propose a high-level synthesis method targeting distributed/shared-register architectures. Our method repeats (1) scheduling/FU binding, (2) register allocation, (3) register binding, and (4) module placement. By feeding back floorplan information from (4) to (1), our method obtains a distributed/shared-register architecture where its scheduling/binding as well as floorplaning are simultaneously optimized. Experimental results show that the area is decreased by 13.2% while maintaining the performance of the circuit equal with that using distributed-register architectures.

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著者

• Togawa Nozomu

  School of Science and Engineering, Waseda University

• Ohtsuki Tatsuo

  School Of Science And Engineering Waseda University

• Kohara Shunitsu

  School of Fundamental Science and Engineering, Waseda University

• Ohchi Akira

  School of Fundamental Science and Engineering, Waseda University

• Yanagisawa Masao

  School of Fundamental Science and Engineering, Waseda University

• Ohtsuki Tatsuo

  School of Fundamental Science and Engineering, Waseda University

関連論文

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• Floorplan-Driven High-Level Synthesis for Distributed/Shared-Register Architectures

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