A Depth-Constrained Technology Mapping Algorithm for Logic-Blocks Composed of Tree-Structured LUTs (Special Section on Selected Papers from the 11th Workshop on Circuits and Systems in Karuizawa)

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概要

• 論文の詳細を見る

• This paper proposes a fast depth-constrained technology mapping algorithm for logic-blocks composed of tree-structured lookup tables. First, we propose a technology mapping algorithm which minimizes the number of logic-blocks if an input Boolean network is a tree. Second, we propose a technology mapping algorithm which minimizes logic depth for any input Boolean network. Finally, we combine those two technology mapping algorithms and propose an algorithm which realizes technology mapping whose depth is bounded by a given upper bound d_c. Experimental results demonstrate the effectiveness and efficiency of the proposed algorithm.

• 社団法人電子情報通信学会の論文
• 1999-03-25

著者

• Togawa N

  Univ. Kitakyushu Kitakyushu‐shi Jpn

• Yanagisawa M

  The Dept. Of Computer Science Waseda University

• Yanagisawa Masao

  Department Of Computer Science Waseda University

• Ohtsuki Tatsuo

  Department Of Computer Science And Engineering Waseda University

• Ohtsuki Tomoaki

  The Department Of Electrical Engineering Science University Of Tokyo

• Ohtsuki T

  Department Of Electrical Engineering Tokyo University Of Science

• Yanagisawa Masao

  Department Of Cardiology Tama-nagayama Hospital Nippon Medical School

• Togawa Nozomu

  Department Of Computer Science And Engineering Waseda University

• ARA Koji

  Department of Electronics, Information and Communication Engineering, Waseda University

• Ara Koji

  Department Of Electronics Information And Communication Engineering Waseda University:(present) Hita

• Yanagisawa Masao

  Department Of Cardiology Nippon Medical School

• Masao Yanagisawa

  School of Fundamental Science and Engineering Waseda University

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