Floorplan-Driven High-Level Synthesis for Distributed/Shared-Register Architectures
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概要
- 論文の詳細を見る
In this paper we propose a high-level synthesis method targeting distributed/shared-register architectures. Our method repeats (1) scheduling/FU binding (2) register allocation (3) register binding and (4) module placement. By feeding back floorplan information from (4) to (1) our method obtains a distributed/shared-register architecture where its scheduling/binding as well as floorplaning are simultaneously optimized. Experimental results show that the area is decreased by 13.2% while maintaining the performance of the circuit equal with that using distributed-register architectures.
- 一般社団法人情報処理学会の論文
- 2008-08-27
著者
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Yanagisawa M
The Dept. Of Computer Science Waseda University
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Yanagisawa Masao
Department Of Computer Science Waseda University
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Nozomu Togawa
Department of Computer Science and Engineering, Waseda University
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Nozomu Togawa
School of Fundamental Science and Engineering Waseda University
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Tatsuo Ohtsuki
School of Fundamental Science and Engineering Waseda University
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Akira Ohchi
School of Fundamental Science and Engineering Waseda University
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Shunitsu Kohara
School of Fundamental Science and Engineering Waseda University
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Masao Yanagisawa
School of Fundamental Science and Engineering Waseda University
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