A Fast Selector-Based Subtract-Multiplication Unit and Its Application to Butterfly Unit

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概要

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• Large-scale network and multimedia application LSIs include application specific arithmetic units. A multiply-accumulator unit or a MAC unit which is one of these optimized units arranges partial products and decreases carry propagations. However, there is no method similar to MAC to execute "subtract-multiplication". In this paper, we propose a high-speed subtract-multiplication unit that decreases latency of a subtract operation by bit-level transformation using selector logics. By using bit-level transformation, its partial products are calculated directly. The proposed subtract-multiplication units can be applied to any types of systems using subtract-multiplications and a butterfly operation in FFT is one of their suitable applications. We apply them effectively to Radix-2 butterfly units and Radix-4 butterfly units. Experimental results show that our proposed operation units using selector logics improves the performance by up to 13.92%, compared to a conventional approach.

• 一般社団法人情報処理学会の論文
• 2011-02-08

著者

• Yanagisawa Masao

  Department Of Computer Science Waseda University

• Nozomu Togawa

  Department of Computer Science and Engineering, Waseda University

• Tatsuo Ohtsuki

  Department of Computer Science and Engineering, Waseda University

• Masao Yanagisawa

  Department of Electronic and Photonic Systems, Waseda University

• Youhei Tsukamoto

  Department of Computer Science and Engineering, Waseda University

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