Performance Analysis of Multi-Pulse Pulse Position Modulation Using Avalanche Photodiode in Optical Intersatellite Links
スポンサーリンク
概要
- 論文の詳細を見る
The bit error rate (BER) performance of multi-pulse pulse position modulation (MPPM) using an avalanche photodiode (APD) is evaluated in optical intersatellite links (ISL's). We derive theoretical expression of BER of MPPM consisting of M slots and P pulses, referred to as (M, P) MPPM with output statistics of the APD which is approximated by Gaussian distribution. The BER performance of (7,2) MPPM and (9,2) MPPM is compared with that of 4-ary PPM under the conditions that bit rate is constant (200Mbits/s) and that bandwidth is limited (slot time period is 2.5ns). It is shown that (9,2) MPPM using the APD can achieve better BER performance than 4-ary PPM using the APD with broadening slot time period by about 10% under the condition that bit rate is constant or with improving bit rate by about 10% under the condition that bandwidth is constant when average photons/nat is somewhat large in achieving BER of 10^lt-9gt.
- 社団法人電子情報通信学会の論文
- 1996-01-25
著者
-
Ohtsuki Tomoaki
The Department Of Electrical Engineering Science University Of Tokyo
-
Sasase Iwao
The Department Of Electrical Engineering Faculty Of Science And Technology Keio University
-
Sasase Iwao
The Dept. Of Electrical Engineering Keio University
-
AOKI Norihito
the Dept. of Electrical Engineering, Keio University
-
Aoki Norihito
The Dept. Of Electrical Engineering Keio University:canon Inc.
-
Ohtsuki Tomoaki
The Dept. Of Electrical Engineering Keio University:the Dept. Of Electrical Engineering Science Univ
-
OHTSUKI Tomoaki
the Department of Computer and Information Science, Keio University
関連論文
- FPGA-Based Reconfigurable Adaptive FEC(System Level Design)(VLSI Design and CAD Algorithms)
- Floorplan-Aware High-Level Synthesis for Generalized Distributed-Register Architectures
- Selective Low-Care Coding : A Means for Test Data Compression in Circuits with Multiple Scan Chains(Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
- A Fast Elliptic Curve Cryptosystem LSI Embedding Word-Based Montgomery Multiplier (System LSIs and Microprocessors, VLSI Design Technology in the Sub-100nm Era)
- A SIMD Instruction Set and Functional Unit Synthesis Algorithm with SIMD Operation Decomposition(Programmable Logic, VLSI, CAD and Layout, Recent Advances in Circuits and Systems-Part 1)
- Sub-operation Parallelism Optimization in SIMD Processor Core Synthesis(Selected Papers from the 17th Workshop on Circuits and Systems in Karuizawa)
- High-Level Power Optimization Based on Thread Partitioning(System Level Design)(VLSI Design and CAD Algorithms)
- A Hardware/Software Cosynthesis Algorithm for Processors with Heterogeneous Datapaths(Selected Papers from the 16th Workshop on Circuits and Systems in Karuizawa)
- A Hardware/Software Partitioning Algorithm for Processor Cores with Packed SIMD-Type Instructions(Design Methodology)(VLSI Design and CAD Algorithms)
- A Retargetable Simulator Generator for DSP Processor Cores with Packed SIMD-type Instructions(Simulation Acceletor)(VLSI Design and CAD Algorithms)
- A Retargetable Simulator Generator for DSP Processor Cores with Packed SIMD-type Instructions
- A Hardware/Software Cosynthesis System for Processor Cores with Content Addressable Memories
- A High-Level Energy-Optimizing Algorithm for System VLSIs Based on Area/Time/Power Estimation(Special Section on VLSI Design and CAD Algorithms)
- An Algorithm and a Flexible Architecture for Fast Block-Matching Motion Estimation(Special Section on VLSI Design and CAD Algorithms)
- C-5 A Software/Hardware Codesign for MPEG Encoder
- High-Level Area/Delay/Power Estimation for Low Power System VLSIs with Gated Clocks(Special Section of Selected Papers from the 14th Workshop on Circuits and Systems in Karuizawa)
- A New Hardware/Software Partitioning Algorithm for DSP Processor Cores with Two Types of Register Files(Special Section on VLSI Design and CAD Algorithms)
- Area and Delay Estimation in Hardware/Software Cosynthesis for Digital Signal Processor Cores(Special Section on VLSI Design and CAD Algorithms)
- An Area/Time Optimizing Algorithm in High-Level Synthesis of Control-Based Hardwares (Special Section on Discrete Mathematics and Its Applications)
- CAM Processor Synthesis Based on Behavioral Descriptions (Special Section on VLSI Design and CAD Algorithms)
- A Hardware / Software Cosynthesis System for Digital Signal Processor Cores with Two Types of Register Files (Special Section of Selected Papers from the 12th Workshop on Circuit and Systems in Karuizawa)
- Equalization for Infrared Wireless Systems Using OOK-CDMA
- Indoor Infrared Wireless Systems Using OOK-CDMA with Decision-Feedback Equalizer on Diffuse Channels
- Trellis Coded Modulation using Partially Overlapped Signal Sets of Non-equiprobable Signaling (Special Issue on Personal Communications)
- Direct-Detection Optical Synchronous CDMA Systems with Interference Canceller Using Group Information Codes (Special Section on Spread Spectrum Techniques and Applications)
- Optical Spread Time CDMA Communication Systems with PPM Signaling
- Performance Analysis of Optical Frequency-Domain Encoding CDMA Enhancement of Frequency Division Multiplexing
- Performance Analysis of Optical Synchronous PPM/CDMA Systems with Interference Canceller Under Number-State Light Field (Special Issue on Optical Access Networks toward Life Enhancement)
- A Two-Level Cache Design Space Exploration System for Embedded Applications
- An L1 Cache Design Space Exploration System for Embedded Applications
- A Built-in Reseeding Technique for LFSR-Based Test Pattern Generation(Timing Verification and Test Generation)(VLSI Design and CAD Algorithms)
- A Built-in Reseeding Technique for LFSR-Based Test Pattern Generation
- A Selective Scan Chain Reconfiguration through Run-Length Coding for Test Data Compression and Scan Power Reduction(Test)(VLSI Design and CAD Algorithms)
- A Hybrid Dictionary Test Data Compression for Multiscan-Based Designs(Test)(VLSI Design and CAD Algorithms)
- Multiple Pre-Rake Filtering Based on the Predicted Channel Impulse Response in the Transmitter and a Rake Combiner in the Receiver for TDD/DS-CDMA Mobile Communication Systems
- A Scan-Based Attack Based on Discriminators for AES Cryptosystems
- X-Handling for Current X-Tolerant Compactors with More Unknowns and Maximal Compaction
- Unified Dual-Radix Architecture for Scalable Montgomery Multiplications in GF(P) and GF(2^n)
- A Unified Test Compression Technique for Scan Stimulus and Unknown Masking Data with No Test Loss
- A Secure Test Technique for Pipelined Advanced Encryption Standard
- Scan-Based Side-Channel Attack against RSA Cryptosystems Using Scan Signatures
- RP-Reconstruncting ARP Strategy for Micro-Cellular Systems
- A Hardware/Software Cosynthesis System for Digital Signal Processor Cores (Special Section on VLSI Design and CAD Algorithms)
- A Depth-Constrained Technology Mapping Algorithm for Logic-Blocks Composed of Tree-Structured LUTs (Special Section on Selected Papers from the 11th Workshop on Circuits and Systems in Karuizawa)
- A Fast Scheduling Algorithm Based on Gradual Time-Frame Reduction for Datapath Synthesis
- An FPGA Layout Reconfiguration Algorithm Based on Global Routes for Engineering Changes in System Design Specifications(Special Section on Discrete Mathematics and Its Applications)
- Computational Complexity Reduction of MLD Based on SINR in MIMO Spatial Multiplexing Systems (Antennas and Propagation)
- Performance Analysis of Multi-Pulse Pulse Position Modulation Using Avalanche Photodiode in Optical Intersatellite Links
- Multibits/Sequence-Period Optical CDMA Receiver with Double Optical Hardlimiters(Spread Spectrum Technologies and Applications)
- State Classification with Array Sensor Using Support Vector Machine for Wireless Monitoring Systems