MIYAOKA Yuichiro | Department of Computer Science, Waseda University
スポンサーリンク
概要
関連著者
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Togawa N
Univ. Kitakyushu Kitakyushu‐shi Jpn
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Togawa Nozomu
The Dept. Of Computer Science Waseda University
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Yanagisawa M
The Dept. Of Computer Science Waseda University
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Yanagisawa Masao
Department Of Computer Science Waseda University
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MIYAOKA Yuichiro
Department of Computer Science, Waseda University
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Ohtsuki Tatsuo
Department Of Computer Science And Engineering Waseda University
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Ohtsuki Tomoaki
The Department Of Electrical Engineering Science University Of Tokyo
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Ohtsuki T
Department Of Electrical Engineering Tokyo University Of Science
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Miyaoka Yuichiro
Department Of Computer Science Waseda University
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Masao Yanagisawa
School of Fundamental Science and Engineering Waseda University
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Ohtsuki Tatsuo
Department of Computer Science and Engineering, Waseda University
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Ohtsuki T
Tokyo Univ. Sci. Noda‐shi Jpn
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TOGAWA Nozomu
Department of Computer Science, Waseda University
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Ohtsuki T
Waseda Univ. Tokyo Jpn
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Togawa Nozomu
Department Of Computer Science And Engineering Waseda University
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Yanagisawa Masao
Department Of Internal Medicine Division Of Cardiology Nippon Medical School Tama-nagayama Hosipital
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Yanagisawa Masao
Department Of Cardiology Tama-nagayama Hospital Nippon Medical School
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Yanagisawa Masao
Department Of Cardiology Nippon Medical School
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Togawa Nozomu
Dept. Of Computer Science Waseda University
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UCHIDA Jumpei
the Dept. of Computer Science, Waseda University
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TACHIKAKE Koichi
Department of Computer Science, Waseda University
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KASAHARA Kyosuke
Department of Electronics, Information and Communication Engineering, Waseda University
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CHOI Jinku
Department of Computer Engineering,Korea Polytechnic University
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Choi J
Korea Univ. Seoul Kor
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Tachikake Koichi
Department Of Computer Science Waseda University:(present Address)ibm
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Kasahara Kyosuke
Department Of Electronics Information And Communication Engineering Waseda University
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Uchida Jumpei
The Dept. Of Computer Science Waseda University
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Shimizu Kazunori
Graduate School Of Information Production And Systems Waseda University
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TOGAWA Nozomu
Dept. of Computer Science, Waseda University
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UCHIDA Jumpei
Dept. of Computer Science, Waseda University
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MIYAOKA Yuichiro
Dept. of Electronics, Information and Communication Engineering, Waseda University
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YANAGISAWA Masao
Dept. of Computer Science, Waseda University
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OHTSUKI Tatsuo
Dept. of Computer Science, Waseda University
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Togawa Nozomu
The Department Of Electronics Information And Communication Engineering Waseda University
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OHTSUKI Tatsuo
the Department of Electronics, Information and Communication Engineering, Waseda University
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YANAGISAWA Masao
the Department of Electronics, Information and Communication Engineering, Waseda University
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KAWAZU Hideki
Department of Computer Science, Waseda University
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UCHIDA Jumpei
Department of Computer Science, Waseda University
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YANAGISAWA Masao
Advanced Research Institute for Science and Engineering, Waseda University
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OHTSUKI Tatsuo
Advanced Research Institute for Science and Engineering, Waseda University
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CHOI Jinku
Korea Polytechnic University
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KATAOKA Yoshiharu
the Department of Electronics, Information and Communication Engineering, Waseda University
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MIYAOKA Yuichiro
the Department of Electronics, Information and Communication Engineering, Waseda University
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Kawazu Hideki
Department Of Computer Science Waseda University
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Ohtsuki Tatsuo
The Department Of Electronics And Communication Engineering School Of Science And Engineering Waseda
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Yanagisawa Masao
Dept. Electronics Waseda Univ.
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Yanagisawa Masao
The Department Of Electronics Information And Communication Engineering Waseda University
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Kataoka Yoshiharu
The Department Of Electronics Information And Communication Engineering Waseda University:(present A
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Choi Jinku
Department Of Computer Engineering Korea Polytechnic University
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Togawa Nozomu
Dept. of Computer Science and Engineering, Waseda University
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YANAGISAWA Masao
the Department of Electronic and Photonic Systems, Waseda University
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TOGAWA Nozomu
the Department of Computer Science and Engineering, Waseda University
著作論文
- FPGA-Based Reconfigurable Adaptive FEC(System Level Design)(VLSI Design and CAD Algorithms)
- A SIMD Instruction Set and Functional Unit Synthesis Algorithm with SIMD Operation Decomposition(Programmable Logic, VLSI, CAD and Layout, Recent Advances in Circuits and Systems-Part 1)
- Sub-operation Parallelism Optimization in SIMD Processor Core Synthesis(Selected Papers from the 17th Workshop on Circuits and Systems in Karuizawa)
- A Hardware/Software Cosynthesis Algorithm for Processors with Heterogeneous Datapaths(Selected Papers from the 16th Workshop on Circuits and Systems in Karuizawa)
- A Hardware/Software Partitioning Algorithm for Processor Cores with Packed SIMD-Type Instructions(Design Methodology)(VLSI Design and CAD Algorithms)
- A Retargetable Simulator Generator for DSP Processor Cores with Packed SIMD-type Instructions(Simulation Acceletor)(VLSI Design and CAD Algorithms)
- A Retargetable Simulator Generator for DSP Processor Cores with Packed SIMD-type Instructions
- Area and Delay Estimation in Hardware/Software Cosynthesis for Digital Signal Processor Cores(Special Section on VLSI Design and CAD Algorithms)