NAKAMURA Yuichi | NEC Corporation

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概要

• NAKAMURA Yuichiの詳細を見る
• 同名の論文著者
• NEC Corporationの論文著者

関連著者

• NAKAMURA Yuichi

  NEC Corporation

• Nakamura Yuichi

  Nec Corp.

• Chen Lei

  Graduate School Of Information Production And Systems Waseda University

• 堀山 貴史

  京都大学大学院情報学研究科

• 堀山 貴史

  埼玉大学情報システム工学科

• KIMURA Shinji

  Graduate School of Information Science, Nara Institute of Science and Technology

• Kimura Shinji

  Graduate School Of Information Production And Systems Waseda University

• 堀山 貴史

  埼玉大学

• HORIYAMA Takashi

  Saitama University

• Horiyama Takashi

  Graduate School Of Informatics Kyoto University

• Yoshimura Takeshi

  Waseda Univ.

• Chen Lei

  Graduate Institute Of Ferrous Technology Pohang University Of Science And Technology

• Kimura Shinji

  Graduate School Of Engineering Nagoya University

• KIMURA Shinji

  Graduate School of Information, Production and Systems, Waseda University

• Yoshimura T

  Ntt Docomo Inc. Yokohama‐shi Jpn

• YOSHIMURA Takeshi

  Waseda University

• YOSHIKAWA Ko

  NEC Corporation

• Nakamura Y

  Nec Corporation

• TAKASHIMA Yasuhiro

  Department of Pediatrics, Kobe University School of Medicine

• Hosokawa Kouhei

  Nec Corporation

• Takashima Yasuhiro

  Department Of Information And Media The University Of Kitakyushu

• Yanagibashi Kunihiko

  Department Of Information And Media The University Of Kitakyushu

• KANAMARU Keisuke

  NEC Corporation

• HAGIHARA Yasuhiko

  NEC Corporation

• INUI Shigeto

  NEC Corporation

• Hosokawa Kouhei

  Nec Corp. Kawasaki‐shi Jpn

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著作論文

• Fast FPGA-Emulation-Based Simulation Environment for Custom Processors(Simulation and Verification,VLSI Design and CAD Algorithms)
• Fine-Grained Power Gating Based on the Controlling Value of Logic Elements
• Fine-grained power gating based on the controlling value of logic gates (VLSI設計技術)
• Fine-grained power gating based on the controlling value of logic gates (システムLSI設計技術)
• A Relocation Method for Circuit Modifications(Circuit Synthesis,VLSI Design and CAD Algorithms)
• An Engineering Change Orders Design Method Based on Patchwork-Like Partitioning for High Performance LSIs(Logic Synthesis, VLSI Design and CAD Algorithms)
• Timing Optimization Methodology Based on Replacing Flip-Flops by Latches(Logic Synthesis)(VLSI Design and CAD Algorithms)
• Hierarchical-Analysis-Based Fast Chip-Scale Power Estimation Method for Large and Complex LSIs(Simulation and Verification,VLSI Design and CAD Algorithms)

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