Fast FPGA-Emulation-Based Simulation Environment for Custom Processors(Simulation and Verification,<Special Section>VLSI Design and CAD Algorithms)

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概要

• 論文の詳細を見る

• This paper describes a new method for the simulation environment for a custom processor. It is generally very hard to develop an accurate simulator for a custom processor rapidly, even if simple instruction-set-level simulator (ISS). The proposed method uses a field-programmable-gate-array emulator with a PCI interface and debugging GUI software on a PC. Since the emulator implements the processor design at the register-transfer or net-list level, the emulation results are almost the same as the results obtained with the actual processor. To support rich debugging functions like those provided by the conventional software simulator, we use a debugging buffer and break-control circuits. Experimental results show that a simulator constructed by the proposed method can be constructed within several hours and that it can break the processor operation at any specified point and observe the internal signals when the emulated system is running at 1-30MHz. The accuracy of the constructed simulator is the same as that of RTL simulation and much higher than that of software ISS simulation. We show that we can provide a fast, accurate, and useful simulator for any processor design specified at the register-transfer level.

• 社団法人電子情報通信学会の論文
• 2006-12-01

著者

• Hosokawa Kouhei

  Nec Corporation

• NAKAMURA Yuichi

  NEC Corporation

• Hosokawa Kouhei

  Nec Corp. Kawasaki‐shi Jpn

• Nakamura Yuichi

  Nec Corp.

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