Timing Optimization Methodology Based on Replacing Flip-Flops by Latches(Logic Synthesis)(<Special Section>VLSI Design and CAD Algorithms)

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概要

• 論文の詳細を見る

• Latch-based circuits have advantages for timing and are widely used for high-speed custom circuits. ASIC design flows, however, are based on circuits with flip-flops. This paper describes a new timing optimization algorithm by replacing the flip-flops in high-end ASICs by latches without changing the functionality of the circuits. Timing is optimized by using a fixed-phase retiming minimizing the impact of clock skew and jitter. A formal equivalence verification method that assures the logical correctness of the latch-replaced circuits is also proposed. Experimental results show that the optimization algorithm decreases the delay of benchmark circuits by as much as 17%.

• 社団法人電子情報通信学会の論文
• 2004-12-01

著者

• NAKAMURA Yuichi

  NEC Corporation

• Yoshimura T

  Ntt Docomo Inc. Yokohama‐shi Jpn

• YOSHIMURA Takeshi

  Waseda University

• Yoshimura Takeshi

  Waseda Univ.

• YOSHIKAWA Ko

  NEC Corporation

• KANAMARU Keisuke

  NEC Corporation

• HAGIHARA Yasuhiko

  NEC Corporation

• INUI Shigeto

  NEC Corporation

• Nakamura Y

  Nec Corporation

• Nakamura Yuichi

  Nec Corp.

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