IKENAGA Takeshi | IPS, Waseda University
スポンサーリンク
概要
関連著者
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IKENAGA Takeshi
IPS, Waseda University
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Ikenaga Takeshi
Graduate School Of Ips Waseda University
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Ikenaga Takeshi
Graduate School Of Information Production And System Waseda University
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Ikenaga Takeshi
Ips Waseda University
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Ishikawa Tatsuyuki
Graduate School Of Information Production And Systems Waseda University
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Ikenaga Takeshi
Waseda Univ.
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HUANG Yiqing
IPS, Waseda University
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Goto Satoshi
Waseda Univ. Jpn
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GOTO Satoshi
IPS, Waseda University
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Liu Qin
Nanjing Univ.
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Huang Yiqing
Graduate School Of Information Production And System Waseda University
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Goto Satoshi
Graduate School Of Information Production And System Waseda University
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Ikenaga Takeshi
Graduate school of Information, Production and Systems, Waseda University
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IKENAGA Takeshi
The Graduate School of Information, Production and Systems, Waseda University
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IKENAGA Takeshi
Graduate School of Fundamental Science and Engineering, Waseda University
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LIU Qin
IPS, Waseda University
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GOTO Satoshi
Graduate School of Information, Production and Systems, Waseda University
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Goto Satoshi
Ips Waseda University
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SHIMIZU Kazunori
IPS, Waseda University
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Shimizu Kazunori
Ips Waseda University
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Goto Satoshi
Graduate School of Infomlation Production and Systems Waseda University
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Liu Zhenyu
Ips Waseda University
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Liu Zhenyu
Tsinghua University
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Ikenaga Takeshi
The Graduate School Of Information Production And Systems Waseda University
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Shimizu Kazunori
Graduate School Of Information Production And Systems Waseda University
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TOGAWA Nozomu
Dept. of Computer Science, Waseda University
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Liu Zhenyu
Kitakyushu Foundation For The Advancement Of Industry Science And Technology
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Togawa Nozomu
Dept. Of Computer Science Waseda University
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LIU Qin
Graduate School of Information, Production, and Systems, WASEDA University
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Huang Yiqing
Ricoh R&d Center
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SONG Yang
Graduate School of Information, Production and Systems, Waseda University
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Song Yang
Graduate School Of Ips Waseda University
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SONG Yang
IPS, Waseda University
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Wu Shuijiong
Ips Waseda University
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FAN Yibo
IPS, Waseda University
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Fan Yibo
Ips Waseda University
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SU Jia
IPS, Waseda University
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Sun Jun
Ips Waseda University
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Togawa Nozomu
Dept. of Computer Science and Engineering, Waseda University
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ISHIKAWA Tatsuyuki
Graduate School of Information, Production and Systems, Waseda University
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HUANG Yiqing
The Graduate School of Information, Production and Systems, Waseda University
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LI Shen
IPS, Waseda University
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MATSUI Masataka
Digital Media SoC Dept., SoC R & D Center, Toshiba Corp.
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Zheng Zhewen
Ips Waseda University
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Li Shen
Waseda Univ. Kitakyushu‐shi Jpn
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Matsui Masataka
Digital Media Soc Dept. Soc R & D Center Toshiba Corp.
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JIN Xiaocong
IPS, Waseda University
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Jin Xiaocong
Ips Waseda University
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WANG Lei
University of Electro-Communications
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TSUNOO Yukiyasu
NEC Corporation
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Wang Qi
Graduate School Of Information Production And Systems Waseda University
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IKENAGA Takeshi
Waseda University
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GOTO Satoshi
Waseda University
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Wang Jun
Graduate School Of Ips Waseda University
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TOGAWA Nozomu
Department of Computer Science, Waseda University
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Liu Qin
Software Institute Of Nanjing University
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ZHENG Zhewen
Graduate School of Information, Production, and Systems, WASEDA University
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LIU Qin
The Graduate School of Information, Production and Systems, Waseda University
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Wu Shuijiong
Graduate School of Information, Production, and Systems, WASEDA University
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SHAO Ming
IPS, Waseda University
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GOTO Satoshi
the Graduate School of Information, Production and Systems, Waseda University
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LI Lingfeng
IPS, Waseda University
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ISHIWATA Shunichi
Digital Media SoC Dept., SoC R & D Center, Toshiba Corp.
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TAKEDA Hideki
Digital Media SoC Dept., SoC R & D Center
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Huang Yiqing
Waseda Univ. Kitakyushu‐shi Jpn
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Huang Yiqing
Ips Waseda University
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SHIMIZU Kazunori
Dept. of Computer Science, Waseda University
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HIRATSUKA Seiichiro
IPS, Waseda University
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USHIKI Shinsuke
IPS, Waseda University
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WANG Lei
IPS, Waseda University
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WANG Jun
IPS, Waseda University
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Goto Satoshi
Waseda Univ.
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WANG Jidong
IPS, Waseda University
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TSUNOO Yukiyasu
Internet Systems Research Laboratories, NEC Corp.
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Wang Lei
Ips Waseda University
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Shao Ming
Ips Waseda University
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Ushiki Shinsuke
Ips Waseda University
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Hiratsuka Seiichiro
Ips Waseda University
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Sun Jun
Institute Of Image Communication And Information Processing Department Of Electronic Engineering Sha
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Wang Jidong
Ips Waseda University
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Takeda Hideki
Digital Media Soc Dept. Soc R & D Center
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LIU Qin
Waseda University
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LIU Zhenyu
IPS, Waseda University
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WU Shuijiong
IPS, Waseda University
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ZHENG Zhewen
IPS, Waseda University
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Wu Shuijiong
Seiee Shanghai Jiao Tong University
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Li Lingfeng
Ips Waseda University
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LIU Peilin
SEIEE, Shanghai Jiao Tong University
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Liu Peilin
Seiee Shanghai Jiao Tong University
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Liu Zhenyu
Tsinghua Univ. Beijing Chn
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WANG Dongsheng
Tsinghua University
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SAKAIDA Shinichi
Science & Technical Research Laboratories NHK (Japan Broadcasting Corporation)
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Togawa Nozomu
Department Of Computer Science And Engineering Waseda University
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Ishiwata Shunichi
Digital Media Soc Dept. Soc R & D Center Toshiba Corp.
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ZHOU Jin
IPS, Waseda University
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Liu Zhenyu
Tsinghua National Laboratory For Information Science And Technology And Department Of Computer Scien
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Wang Dongsheng
Tsinghua National Laboratory For Information Science And Technology And Department Of Computer Scien
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Zhou Jin
Ips Waseda University
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Sun Lei
Ips Waseda University
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JIN Xiaocong
Institute of Image Communication and Information Processing, Shanghai Jiaotong University
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Sakaida Shinichi
Science & Technology Research Laboratories Nhk
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SUN Lei
IPS, Waseda University
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Goto Satoshi
The Graduate School Of Information Production And Systems Waseda University
著作論文
- VLSI Oriented Fast Motion Estimation Algorithm Based on Pixel Difference, Block Overlapping and Motion Feature Analysis
- Efficient Fully-Parallel LDPC Decoder Design with Improved Simplified Min-Sum Algorithms(VLSI Architecture for Communication/Server Systems,VLSI Technology toward Frontiers of New Market)
- Power-Efficient LDPC Decoder Architecture Based on Accelerated Message-Passing Schedule(VLSI Architecture,VLSI Design and CAD Algorithms)
- Partially-Parallel LDPC Decoder Achieving High-Efficiency Message-Passing Schedule(Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
- Reconfigurable Adaptive FEC System Based on Reed-Solomon Code with Interleaving(Adaptive Signal Processing, Recent Advances in Circuits and Systems-Part 1)
- Lossless VLSI Oriented Full Computation Reusing Algorithm for H.264/AVC Fractional Motion Estimation(Selected Papers from the 19th Workshop on Circuits and Systems in Karuizawa)
- D-11-18 An Edge Information Based Block Size Decision Method for Intra Mode Decision in H.264/AVC
- D-11-19 Multi-Stage Based Inter Mode Decision Algorithm in H.264/AVC
- D-11-21 Macroblock Level Rate Control for H.264/AVC Based on Model Parameter Update and Weighted Reference Calculation
- D-11-20 Bayesian Decision Based All-Zero Block Detection Algorithm in H.264/AVC
- A-4-15 Cross Low Pass Filter Based Subsampling Algorithm for H.264/AVC Motion Estimation
- A Fine-Grain Scalable and Low Memory Cost Variable Block Size Motion Estimation Architecture for H.264/AVC(Integrated Electronics)
- A VLSI Array Processing Oriented Fast Fourier Transform Algorithm and Hardware Implementation(VLSI Architecture, VLSI Design and CAD Algorithms)
- Content-Based Complexity Reduction Methods for MPEG-2 to H.264 Transcoding(Advanced Image Technology)
- A Hardware Implementation of a Content-Based Motion Estimation Algorithm for Real-Time MPEG-4 Video Coding(Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
- Low Power LDPC Code Decoder Architecture Based on Intermediate Message Compression Technique
- A 41mW VGA【triple bond】fps Quadtree Video Encoder for Video Surveillance Systems
- Variable Block Size Motion Vector Retrieval Schemes for H.264 Inter Frame Error Concealment
- Highly Parallel Fractional Motion Estimation Engine for Super Hi-Vision 4k×4k@60fps
- A High-Speed Design of Montgomery Multiplier
- Reconfigurable Variable Block Size Motion Estimation Architecture for Search Range Reduction Algorithm
- An Unequal Secure Encryption Scheme for H.264/AVC Video Compression Standard
- Adaptive Sub-Sampling Based Reconfigurable SAD Tree Architecture for HDTV Application
- Hardware-Oriented Early Detection Algorithms for 4×4 and 8×8 All-Zero Blocks in H.264
- VLSI Oriented Fast Motion Estimation Algorithm Based on Pixel Difference, Block Overlapping and Motion Feature Analysis
- Macroblock Feature Based Complexity Reduction for H.264/AVC Motion Estimation
- Macroblock and Motion Feature Analysis to H.264/AVC Fast Inter Mode Decision
- Edge Block Detection and Motion Vector Information Based Fast VBSME Algorithm
- Parallel Improved HDTV720p Targeted Propagate Partial SAD Architecture for Variable Block Size Motion Estimation in H.264/AVC
- A-4-18 Integer Search Position Based Fast Motion Estimation in H.264/AVC
- Constant Bit-Rate Multi-Stage Rate Control for Rate-Distortion Optimized H.264/AVC Encoders
- Architecture and Circuit Optimization of Hardwired Integer Motion Estimation Engine for H.264/AVC
- Highly Parallel and Fully Reused H.264/AVC High Profile Intra Predictor Generation Engine for Super Hi-Vision 4k×4k@60fps
- Fast H.264/AVC DIRECT Mode Decision Based on Mode Selection and Predicted Rate-Distortion Cost
- Content Based Coarse to Fine Adaptive Interpolation Filter for High Resolution Video Coding