GOTO Satoshi | Waseda University

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概要

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著作論文

D-11-14 A Mode Reduction Based Fast Integer Motion Estimation Algorithm for HDTV
A LOW-POWER AND PERFORMANCE-AWARE DVB-S2 LDPC DECODER WITH LAYERED SCHEDULING
A Macroblock Homogeneity Detection Method and its Application for Block Size Decision in H.264/AVC
Content-Based Motion Estimation with Extended Temporal-Spatial Analysis(Image Processing and Multimedia Systems, Recent Advances in Circuits and Systems-Part 1)
Permutation Network for Reconfigurable LDPC Decoder Based on Banyan Network
Implementation of LDPC decoder for 802.16e (情報理論)
A High Performance and Low Bandwidth Multi-Standard Motion Compensation Design for HD Video Decoder
A 48 Cycles/MB H.264/AVC Deblocking Filter Architecture for Ultra High Definition Applications
High Throughput VLSI Architecture of a Fast Mode Decision Algorithm for H.264/AVC Intra Encoding
Adaptive Sub-Sampling Based Reconfigurable SAD Tree Architecture for HDTV Application
A-4-33 High Throughput Rate-1/2 Partially-Parallel Irregular LDPC Decoder
A Bandwidth Optimized, 64 Cycles/MB Joint Parameter Decoder Architecture for Ultra High Definition H.264/AVC Applications
Voltage and Level-Shifter Assignment Driven Floorplanning
Generic Permutation Network for QC-LDPC Decoder
ROI based Computational Complexity Reduction Scheme for H.264/AVC Encoder
Multiple Region-of-Interest Based H.264 Encoder with a Detection Architecture in Macroblock Level Pipelining
A 530Mpixels/s Intra Prediction Architecture for Ultra High Definition H.264/AVC Encoder
Greedy Optimization Algorithm for the Power/Ground Network Design to Satisfy the Voltage Drop Constraint
Cache Based Motion Compensation Architecture for Quad-HD H.264/AVC Video Decoder
A 115mW 1Gbps QC-LDPC Decoder ASIC for WiMAX in 65nm CMOS
A 98GMACs/W 32-Core Vector Processor in 65nm CMOS
A 6.72-Gb/s 8 pJ/bit/iteration IEEE 802.15.3c LDPC Decoder Chip
Watermarking for HDR Image Robust to Tone Mapping
Greedy Algorithm for the On-Chip Decoupling Capacitance Optimization to Satisfy the Voltage Drop Constraint
Cluster Generation and Network Component Insertion for Topology Synthesis of Application-Specific Network-on-Chips

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