Chen Zhixiang | Waseda Univ. Kitakyushu‐shi Jpn
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概要
関連著者
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Chen Zhixiang
Waseda Univ. Kitakyushu‐shi Jpn
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Zhao Xiongxin
Waseda Univ. Kitakyushu‐shi Jpn
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Peng Xiao
Waseda Univ. Kitakyushu‐shi Jpn
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Chen Zhixiang
Graduate School Of Information Production And Systems Waseda University
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Goto Satoshi
Graduate School Of Information Production And System Waseda University
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CHEN Zhixiang
Graduate School of Information, Production and Systems, Waseda University
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GOTO Satoshi
Graduate School of Information, Production and Systems, Waseda University
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Goto Satoshi
Waseda Univ. Jpn
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Zhao Xiongxin
Graduate School Of Information Production And Systems Waseda University
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Peng Xiao
Graduate School Of Information Production And Systems Waseda University
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Xiongxin Zhao
School of Information, Production and Systems, Waseda University
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Goto Satoshi
Graduate School of Infomlation Production and Systems Waseda University
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Goto Satoshi
Graduate School Of Information Production And Systems Waseda University
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GOTO Satoshi
Waseda University
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Zhou Dajiang
Waseda Univ. Kitakyushu‐shi Jpn
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PENG Xiao
Graduate School of Information, Production and Systems, Waseda University
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ZHAO Xiongxin
Graduate School of Information, Production and Systems, Waseda University
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Zhou Dajiang
Graduate School Of Information Production And Systems Waseda University
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MAEHARA Fumiaki
Department of Science and Engineering, Waseda University
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Xie Qian
Graduate School Of Information Production And Systems Waseda University
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Goto Satoshi
Waseda Univ.
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Maehara Fumiaki
Waseda Univ. Tokyo Jpn
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Maehara Fumiaki
Department Of Radiology School Of Medicine Fukuoka University
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Maehara Fumiaki
Department Of Science And Engineering Waseda University
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Zhao Xiongxin
Waseda University
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Okamura Leona
Graduate School Of Information Production And System Waseda University
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Chen Zhixiang
Waseda University
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Peng Xiao
Waseda University
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Zhou Dajiang
Waseda University
著作論文
- A LOW-POWER AND PERFORMANCE-AWARE DVB-S2 LDPC DECODER WITH LAYERED SCHEDULING
- A Sorting-based Architecture of Finding the First Two Minimum Values
- A high-parallelism reconfigurable permutation network for IEEE 802.11n/803.16e LDPC decoder (情報理論)
- Permutation Network for Reconfigurable LDPC Decoder Based on Banyan Network
- Implementation of LDPC decoder for 802.16e (情報理論)
- An multi-rate LDPC decoder system on FPGA (情報理論)
- Generic Permutation Network for QC-LDPC Decoder
- A Sorting-based Architecture of Finding the First Two Minimum Values
- DVB-T2 LDPC Decoder with Perfect Conflict Resolution (System LSI Design Methodology Vol.5)
- A 115mW 1Gbps QC-LDPC Decoder ASIC for WiMAX in 65nm CMOS
- A 6.72-Gb/s 8 pJ/bit/iteration IEEE 802.15.3c LDPC Decoder Chip
- DVB-T2 LDPC Decoder with Perfect Conflict Resolution
- DVB-T2 LDPC Decoder with Perfect Conflict Resolution