A 115mW 1Gbps QC-LDPC Decoder ASIC for WiMAX in 65nm CMOS
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概要
- 論文の詳細を見る
Structured quasi-cyclic low-density parity-check (QC-LDPC) code is a part of many emerging wireless communication standards, such as WiMAX, WiFi and WPAN. This paper presents a high parallel decoder architecture for the QC-LDPC codes and the corresponding decoder ASIC for WiMAX system. Through utilizing the proposed fully parallel layered scheduling architecture, the decoder chip saves 22.2% memory bits and takes 24〜48 clock cycles per iteration for different code rates. It occupies 3.36 mm^2 in SMIC 65nm CMOS, and realizes 1Gbps (1056Mbps) throughput at 1.2V, 110MHz and 10 iterations with the power 115mW and power efficiency 10.9pJ/bit/iteration. The energy/bit/iteration reduces 63.6% in normalized comparison with the state-of-art publication.
- 2012-01-12
著者
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CHEN Zhixiang
Graduate School of Information, Production and Systems, Waseda University
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GOTO Satoshi
Graduate School of Information, Production and Systems, Waseda University
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GOTO Satoshi
Waseda University
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Goto Satoshi
Waseda Univ. Jpn
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Peng Xiao
Waseda Univ. Kitakyushu‐shi Jpn
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Zhou Dajiang
Waseda Univ. Kitakyushu‐shi Jpn
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Zhao Xiongxin
Waseda Univ. Kitakyushu‐shi Jpn
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Chen Zhixiang
Waseda Univ. Kitakyushu‐shi Jpn
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Zhou Dajiang
Graduate School Of Information Production And Systems Waseda University
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Zhao Xiongxin
Graduate School Of Information Production And Systems Waseda University
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Chen Zhixiang
Graduate School Of Information Production And Systems Waseda University
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Peng Xiao
Graduate School Of Information Production And Systems Waseda University
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Goto Satoshi
Graduate School Of Information Production And System Waseda University
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Xiongxin Zhao
School of Information, Production and Systems, Waseda University
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Goto Satoshi
Graduate School of Infomlation Production and Systems Waseda University
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