DVB-T2 LDPC Decoder with Perfect Conflict Resolution
スポンサーリンク
概要
- 論文の詳細を見る
Currently most of LDPC decoders are implemented with the so-called layered algorithm for its implementation efficiency and relatively high decoding performance. However, not all of structured LDPC codes can be implemented with the layered algorithm directly because of the message updating conflicts within layers in the a-posteriori information memory. In this paper we focus on the resolution of this kind of conflicts for DVB-T2 LDPC decoders. Unlike the previous resolutions, we directly implement the layered algorithm without modifying the parity-check matrices (PCM) or the decoding algorithm. DVB-T2 LDPC decoder architecture is also proposed in this paper with two new techniques which guarantee conflict-free layered decoding. The PCM Rearrange technique reduces the number of conflicts and eliminates all of data dependency problems between layers to ensure high pipeline efficiency. The Layer Division technique deals with all remaining conflicts with a well-designed decoding schedule. Experiment results show that compared to state-of-the-art works we achieve a slight error-correcting performance gain for DVB-T2 LDPC codes.
著者
-
Peng Xiao
Waseda Univ. Kitakyushu‐shi Jpn
-
Zhou Dajiang
Waseda Univ. Kitakyushu‐shi Jpn
-
Zhao Xiongxin
Waseda Univ. Kitakyushu‐shi Jpn
-
Chen Zhixiang
Waseda Univ. Kitakyushu‐shi Jpn
-
Goto Satoshi
Waseda Univ.
-
Chen Zhixiang
Waseda University
-
Zhao Xiongxin
Waseda University
関連論文
- D-11-14 A Mode Reduction Based Fast Integer Motion Estimation Algorithm for HDTV
- A LOW-POWER AND PERFORMANCE-AWARE DVB-S2 LDPC DECODER WITH LAYERED SCHEDULING
- Region-of-Interest based Preprocessing for H.264/AVC Encoding
- Fast Inter Mode Decision Algorithm Based on Residual Feature
- A Sorting-based Architecture of Finding the First Two Minimum Values
- Content-Based Motion Estimation with Extended Temporal-Spatial Analysis(Image Processing and Multimedia Systems, Recent Advances in Circuits and Systems-Part 1)
- A high-parallelism reconfigurable permutation network for IEEE 802.11n/803.16e LDPC decoder (情報理論)
- Permutation Network for Reconfigurable LDPC Decoder Based on Banyan Network
- Implementation of LDPC decoder for 802.16e (情報理論)
- An multi-rate LDPC decoder system on FPGA (情報理論)
- An Efficient Motion Vector Coding Scheme Based on Prioritized Reference Decision
- A High Performance and Low Bandwidth Multi-Standard Motion Compensation Design for HD Video Decoder
- A 48 Cycles/MB H.264/AVC Deblocking Filter Architecture for Ultra High Definition Applications
- D-11-17 MOTION CORRELATION ADAPTION BASED INTER MODE DECISION ALGORITHM FOR H.264/AVC
- High Throughput VLSI Architecture of a Fast Mode Decision Algorithm for H.264/AVC Intra Encoding
- Adaptive Sub-Sampling Based Reconfigurable SAD Tree Architecture for HDTV Application
- A-4-33 High Throughput Rate-1/2 Partially-Parallel Irregular LDPC Decoder
- A Bandwidth Optimized, 64 Cycles/MB Joint Parameter Decoder Architecture for Ultra High Definition H.264/AVC Applications
- Generic Permutation Network for QC-LDPC Decoder
- ROI based Computational Complexity Reduction Scheme for H.264/AVC Encoder
- A Sorting-based Architecture of Finding the First Two Minimum Values
- A 530Mpixels/s Intra Prediction Architecture for Ultra High Definition H.264/AVC Encoder
- Greedy Optimization Algorithm for the Power/Ground Network Design to Satisfy the Voltage Drop Constraint
- Cache Based Motion Compensation Architecture for Quad-HD H.264/AVC Video Decoder
- DVB-T2 LDPC Decoder with Perfect Conflict Resolution (System LSI Design Methodology Vol.5)
- A 115mW 1Gbps QC-LDPC Decoder ASIC for WiMAX in 65nm CMOS (集積回路・集積回路とアーキテクチャの協創 : ノーマリオフコンピューティングによる低消費電力化への挑戦)
- A 115mW 1Gbps QC-LDPC Decoder ASIC for WiMAX in 65nm CMOS
- A 98GMACs/W 32-Core Vector Processor in 65nm CMOS
- A 6.72-Gb/s 8 pJ/bit/iteration IEEE 802.15.3c LDPC Decoder Chip
- Watermarking for HDR Image Robust to Tone Mapping
- DVB-T2 LDPC Decoder with Perfect Conflict Resolution
- DVB-T2 LDPC Decoder with Perfect Conflict Resolution
- Greedy Algorithm for the On-Chip Decoupling Capacitance Optimization to Satisfy the Voltage Drop Constraint
- Bidirectional Local Template Patterns: An Effective and Discriminative Feature for Pedestrian Detection
- Joint Feature Based Rain Detection and Removal from Videos
- A High Performance HEVC De-Blocking Filter and SAO Architecture for UHDTV Decoder