Content-Based Motion Estimation with Extended Temporal-Spatial Analysis(Image Processing and Multimedia Systems, <Special Section>Recent Advances in Circuits and Systems-Part 1)
スポンサーリンク
概要
- 論文の詳細を見る
In adaptive motion estimation, spatial-temporal correlation based motion type inference has been recognized as an effective way to guide the motion estimation strategy adjustment according to video contents. However, the complexity and the reliability of those methods remain two crucial problems. In this paper, a motion vector field model is introduced as the basis for a new spatial-temporal correlation based motion type inference method. For each block, Full Search with Adaptive Search Window (ASW) and Three Step Search (TSS), as two search strategy can-didates, can be employed alternatively. Simulation results show that the proposed method can constantly reduce the dynamic computational cost to as low as 3% to 4% of that of Full Search (FS), while remaining a closer approximation to FS in terms of visual quality than other fast algorithms for various video sequences. Due to its efficiency and reliability, this method is expected to be a favorable contribution to the mobile video communication where low power real-time video coding is necessary.
- 社団法人電子情報通信学会の論文
- 2005-07-01
著者
-
GOTO Satoshi
IPS, Waseda University
-
IKENAGA Takeshi
Waseda University
-
GOTO Satoshi
Waseda University
-
Ikenaga Takeshi
Waseda Univ.
-
Ikenaga Takeshi
Graduate School Of Ips Waseda University
-
Ikenaga Takeshi
Ips Waseda University
-
Goto Satoshi
Ips Waseda University
-
LI Shen
Waseda University
-
JIANG Yong
Waseda University
-
Li Shen
Waseda Univ. Kitakyushu‐shi Jpn
-
Goto Satoshi
Waseda Univ.
-
Ikenaga Takeshi
The Graduate School Of Information Production And Systems Waseda University
関連論文
- VLSI Oriented Fast Motion Estimation Algorithm Based on Pixel Difference, Block Overlapping and Motion Feature Analysis
- BS-12-19 A Fast Block Type Decision Algorithm for H.264/AVC Intra Prediction(BS-12. Network Planning, Control, and Management)
- D-11-50 A Novel Fast Block Type Decision Algorithm for Intra Prediction in H.264/AVC High Profile
- D-11-14 A Mode Reduction Based Fast Integer Motion Estimation Algorithm for HDTV
- A-16-2 A Fast Mode Decision Algorithm for H.264/AVC Intra Prediction
- A novel fast block type decision algorithm for intra prediction in H.264/AVC high profile (第21回 回路とシステム軽井沢ワークショップ論文集) -- (動画像符号化(1))
- A LOW-POWER AND PERFORMANCE-AWARE DVB-S2 LDPC DECODER WITH LAYERED SCHEDULING
- Region-of-Interest based Preprocessing for H.264/AVC Encoding
- A Macroblock Homogeneity Detection Method and its Application for Block Size Decision in H.264/AVC
- Fast Inter Mode Decision Algorithm Based on Residual Feature
- Efficient Fully-Parallel LDPC Decoder Design with Improved Simplified Min-Sum Algorithms(VLSI Architecture for Communication/Server Systems,VLSI Technology toward Frontiers of New Market)
- Power-Efficient LDPC Decoder Architecture Based on Accelerated Message-Passing Schedule(VLSI Architecture,VLSI Design and CAD Algorithms)
- Partially-Parallel LDPC Decoder Achieving High-Efficiency Message-Passing Schedule(Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
- Reconfigurable Adaptive FEC System Based on Reed-Solomon Code with Interleaving(Adaptive Signal Processing, Recent Advances in Circuits and Systems-Part 1)
- BS-12-18 A Novel Hardware-Friendly Regular 3-Step Integer Motion Estimation Algorithm for H.264/AVC(BS-12. Network Planning, Control, and Management)
- A-16-11 Level C+ Bandwidth Reduction Method for MPEG-2 to H.264 Transcoding
- A-16-1 Group-Based Prediction Scheme on Multiple Reference Frame Fractional Motion Estimation in H.264/AVC
- Lossless VLSI Oriented Full Computation Reusing Algorithm for H.264/AVC Fractional Motion Estimation(Selected Papers from the 19th Workshop on Circuits and Systems in Karuizawa)
- D-11-70 Adaptive Spatial EC based on Numerical Measures of Edge Statistical Model
- An adaptive error concealment order in H.264/AVC (VLSI設計技術)
- An adaptive error concealment order in H.264/AVC (集積回路)
- D-11-18 An Edge Information Based Block Size Decision Method for Intra Mode Decision in H.264/AVC
- D-11-19 Multi-Stage Based Inter Mode Decision Algorithm in H.264/AVC
- D-11-21 Macroblock Level Rate Control for H.264/AVC Based on Model Parameter Update and Weighted Reference Calculation
- D-11-20 Bayesian Decision Based All-Zero Block Detection Algorithm in H.264/AVC
- A-4-15 Cross Low Pass Filter Based Subsampling Algorithm for H.264/AVC Motion Estimation
- BS-12-20 VLSI Design of Level C Bandwidth Reduction Scheme for MPEG-2 to H.264/AVC Transcoding(BS-12. Network Planning, Control, and Management)
- Lossy Strict Multilevel Successive Elimination Algorithm for Fast Motion Estimation(Selected Papers from the 19th Workshop on Circuits and Systems in Karuizawa)
- Low-Power Partial Distortion Sorting Fast Motion Estimation Algorithms and VLSI Implementations(Advanced Image Technology)
- Motion content based search range prediction in variable block size motion estimation (第20回 回路とシステム軽井沢ワークショップ論文集) -- (映像応用)
- A Fine-Grain Scalable and Low Memory Cost Variable Block Size Motion Estimation Architecture for H.264/AVC(Integrated Electronics)
- A VLSI Architecture for Variable Block Size Motion Estimation in H.264/AVC with Low Cost Memory Organization(VLSI Architecture,VLSI Design and CAD Algorithms)
- Scalable VLSI Architecture for Variable Block Size Integer Motion Estimation in H.264/AVC(Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
- 261MHz Parallel Tree Architecture for Full Search Variable Block Size Motion Estimation in H.264/AVC
- 261MHz Parallel Tree Architecture for Full Search Variable Block Size Motion Estimation in H.264/AVC
- A strict successive elimination algorithm for fast motion estimation (映像信号処理)
- A VLSI Array Processing Oriented Fast Fourier Transform Algorithm and Hardware Implementation(VLSI Architecture, VLSI Design and CAD Algorithms)
- Geometrical, Physical and Text/Symbol Analysis Based Approach of Traffic Sign Detection System(Advanced Image Technology)
- A Contour-Based Robust Algorithm for Text Detection in Color Images(Image Recognition, Computer Vision)
- Content-Based Complexity Reduction Methods for MPEG-2 to H.264 Transcoding(Advanced Image Technology)
- A Hardware Implementation of a Content-Based Motion Estimation Algorithm for Real-Time MPEG-4 Video Coding(Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
- A Highly Parallel Architecture for Deblocking Filter in H.264/AVC(Parallel and/or Distributed Processing Systems, Recent Advances in Circuits and Systems-Part1)
- Content-Based Motion Estimation with Extended Temporal-Spatial Analysis(Image Processing and Multimedia Systems, Recent Advances in Circuits and Systems-Part 1)
- A low-cost LSI design of AES against DPA attack by hiding power information (第21回 回路とシステム軽井沢ワークショップ論文集) -- (実現技術)
- An efficient encryption scheme for H.264 format video streams (第20回 回路とシステム軽井沢ワークショップ論文集) -- (画像応用)
- A high-speed design of Montgomery multiplier (第20回 回路とシステム軽井沢ワークショップ論文集) -- (システム実現技術)
- Low Power LDPC Code Decoder Architecture Based on Intermediate Message Compression Technique
- A 41mW VGA【triple bond】fps Quadtree Video Encoder for Video Surveillance Systems
- Standard Deviation and Intra Prediction Mode Based Adaptive Spatial Error Concealment (SEC) in H.264/AVC
- Variable Block Size Motion Vector Retrieval Schemes for H.264 Inter Frame Error Concealment
- Permutation Network for Reconfigurable LDPC Decoder Based on Banyan Network
- Implementation of LDPC decoder for 802.16e (情報理論)
- Highly Parallel Fractional Motion Estimation Engine for Super Hi-Vision 4k×4k@60fps
- A High Performance and Low Bandwidth Multi-Standard Motion Compensation Design for HD Video Decoder
- A 48 Cycles/MB H.264/AVC Deblocking Filter Architecture for Ultra High Definition Applications
- A High-Speed Design of Montgomery Multiplier
- Reconfigurable Variable Block Size Motion Estimation Architecture for Search Range Reduction Algorithm
- An Unequal Secure Encryption Scheme for H.264/AVC Video Compression Standard
- D-11-17 MOTION CORRELATION ADAPTION BASED INTER MODE DECISION ALGORITHM FOR H.264/AVC
- High Throughput VLSI Architecture of a Fast Mode Decision Algorithm for H.264/AVC Intra Encoding
- Adaptive Sub-Sampling Based Reconfigurable SAD Tree Architecture for HDTV Application
- Hardware-Oriented Early Detection Algorithms for 4×4 and 8×8 All-Zero Blocks in H.264
- VLSI Oriented Fast Motion Estimation Algorithm Based on Pixel Difference, Block Overlapping and Motion Feature Analysis
- Macroblock Feature Based Complexity Reduction for H.264/AVC Motion Estimation
- Macroblock and Motion Feature Analysis to H.264/AVC Fast Inter Mode Decision
- Adaptive Search Range Algorithms for Variable Block Size Motion Estimation in H.264/AVC
- Content-Aware Fast Motion Estimation for H.264/AVC
- Edge Block Detection and Motion Vector Information Based Fast VBSME Algorithm
- Parallel Improved HDTV720p Targeted Propagate Partial SAD Architecture for Variable Block Size Motion Estimation in H.264/AVC
- A-4-18 Integer Search Position Based Fast Motion Estimation in H.264/AVC
- Constant Bit-Rate Multi-Stage Rate Control for Rate-Distortion Optimized H.264/AVC Encoders
- A High Performance Partially-Parallel Irregular LDPC Decoder Based on Sum-Delta Message Passing Schedule
- A-4-33 High Throughput Rate-1/2 Partially-Parallel Irregular LDPC Decoder
- A Bandwidth Optimized, 64 Cycles/MB Joint Parameter Decoder Architecture for Ultra High Definition H.264/AVC Applications
- An Ultra-Low Bandwidth Design Method for MPEG-2 to H.264/AVC Transcoding
- Voltage and Level-Shifter Assignment Driven Floorplanning
- A-6-12 Prediction-based Center-bias Fast Fractional Motion Estimation Algorithm for H.264/AVC
- Generic Permutation Network for QC-LDPC Decoder
- Architecture and Circuit Optimization of Hardwired Integer Motion Estimation Engine for H.264/AVC
- ROI based Computational Complexity Reduction Scheme for H.264/AVC Encoder
- Highly Parallel and Fully Reused H.264/AVC High Profile Intra Predictor Generation Engine for Super Hi-Vision 4k×4k@60fps
- Multiple Region-of-Interest Based H.264 Encoder with a Detection Architecture in Macroblock Level Pipelining
- A 530Mpixels/s Intra Prediction Architecture for Ultra High Definition H.264/AVC Encoder
- Optimized 2-D SAD Tree Architecture of Integer Motion Estimation for H.264/AVC
- Greedy Optimization Algorithm for the Power/Ground Network Design to Satisfy the Voltage Drop Constraint
- Cache Based Motion Compensation Architecture for Quad-HD H.264/AVC Video Decoder
- A Novel Cache Replacement Policy via Dynamic Adaptive Insertion and Re-Reference Prediction
- A 115mW 1Gbps QC-LDPC Decoder ASIC for WiMAX in 65nm CMOS
- Fast H.264/AVC DIRECT Mode Decision Based on Mode Selection and Predicted Rate-Distortion Cost
- Content Based Coarse to Fine Adaptive Interpolation Filter for High Resolution Video Coding
- A 98GMACs/W 32-Core Vector Processor in 65nm CMOS
- A 6.72-Gb/s 8 pJ/bit/iteration IEEE 802.15.3c LDPC Decoder Chip
- Watermarking for HDR Image Robust to Tone Mapping
- DVB-T2 LDPC Decoder with Perfect Conflict Resolution
- DVB-T2 LDPC Decoder with Perfect Conflict Resolution
- Greedy Algorithm for the On-Chip Decoupling Capacitance Optimization to Satisfy the Voltage Drop Constraint
- Low-Complexity Coarse-Level Mode-Mapping Based H.264/AVC to H.264/SVC Spatial Transcoding for Video Conferencing
- Cluster Generation and Network Component Insertion for Topology Synthesis of Application-Specific Network-on-Chips
- Bidirectional Local Template Patterns: An Effective and Discriminative Feature for Pedestrian Detection
- Joint Feature Based Rain Detection and Removal from Videos