DVB-T2 LDPC Decoder with Perfect Conflict Resolution (System LSI Design Methodology Vol.5)
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関連論文
- A LOW-POWER AND PERFORMANCE-AWARE DVB-S2 LDPC DECODER WITH LAYERED SCHEDULING
- A Sorting-based Architecture of Finding the First Two Minimum Values
- A high-parallelism reconfigurable permutation network for IEEE 802.11n/803.16e LDPC decoder (情報理論)
- Permutation Network for Reconfigurable LDPC Decoder Based on Banyan Network
- Implementation of LDPC decoder for 802.16e (情報理論)
- An multi-rate LDPC decoder system on FPGA (情報理論)
- Generic Permutation Network for QC-LDPC Decoder
- A Sorting-based Architecture of Finding the First Two Minimum Values
- DVB-T2 LDPC Decoder with Perfect Conflict Resolution (System LSI Design Methodology Vol.5)
- A 115mW 1Gbps QC-LDPC Decoder ASIC for WiMAX in 65nm CMOS (集積回路・集積回路とアーキテクチャの協創 : ノーマリオフコンピューティングによる低消費電力化への挑戦)
- A 115mW 1Gbps QC-LDPC Decoder ASIC for WiMAX in 65nm CMOS
- A 6.72-Gb/s 8 pJ/bit/iteration IEEE 802.15.3c LDPC Decoder Chip
- DVB-T2 LDPC Decoder with Perfect Conflict Resolution
- DVB-T2 LDPC Decoder with Perfect Conflict Resolution