Implementation of LDPC decoder for 802.16e (情報理論)

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概要

• 論文の詳細を見る

• The implementation complexity of the decoder for Low-density Parity-check Codes (LDPC) is dictated by memory and interconnection requirements. In this paper, we investigate the approaches to realize Turbo Decoding Message Passing (TDMP) algorithm. We compare the performance and implementation complexity of original approach, Jacobian approach, normalized min-sum approach and offset min-sum approach which are targeted for Quasi-Cyclic (QC) LDPC code defined in IEEE802.16e standard. The normalized and offset approaches are more suitable for hardware implementation, which are realized on the FPGA.

• 社団法人電子情報通信学会の論文
• 2009-09-22

著者

• PENG Xiao

  Graduate School of Information, Production and Systems, Waseda University

• CHEN Zhixiang

  Graduate School of Information, Production and Systems, Waseda University

• ZHAO Xiongxin

  Graduate School of Information, Production and Systems, Waseda University

• GOTO Satoshi

  Graduate School of Information, Production and Systems, Waseda University

• GOTO Satoshi

  Waseda University

• Goto Satoshi

  Waseda Univ. Jpn

• Goto Satoshi

  Graduate School Of Information Production And Systems Waseda University

• Peng Xiao

  Waseda Univ. Kitakyushu‐shi Jpn

• Zhao Xiongxin

  Waseda Univ. Kitakyushu‐shi Jpn

• Chen Zhixiang

  Waseda Univ. Kitakyushu‐shi Jpn

• Zhao Xiongxin

  Graduate School Of Information Production And Systems Waseda University

• Chen Zhixiang

  Graduate School Of Information Production And Systems Waseda University

• Peng Xiao

  Graduate School Of Information Production And Systems Waseda University

• Goto Satoshi

  Graduate School Of Information Production And System Waseda University

• Xiongxin Zhao

  School of Information, Production and Systems, Waseda University

• Goto Satoshi

  Graduate School of Infomlation Production and Systems Waseda University

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