A LOW-POWER AND PERFORMANCE-AWARE DVB-S2 LDPC DECODER WITH LAYERED SCHEDULING

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概要

• 論文の詳細を見る

• In this paper we propose an LDPC decoder for DVB-S2 with layered decoding schedule. A particular data updating mechanism for DVB-S2 is introduced to avoid all data updating conflicts without any approximation which worsens the BER performance of decoding. The proposed decoder utilizes the most popular partial-parallel layered decoder architecture and can achieve a decoding throughput larger than 105Mbps at 300MHz with acceptable hardware and clock overhead. Moreover, the proposed architecture shows great potential for performance-aware and low-power design.

• 2010-09-14

著者

• PENG Xiao

  Graduate School of Information, Production and Systems, Waseda University

• CHEN Zhixiang

  Graduate School of Information, Production and Systems, Waseda University

• ZHAO Xiongxin

  Graduate School of Information, Production and Systems, Waseda University

• GOTO Satoshi

  Graduate School of Information, Production and Systems, Waseda University

• GOTO Satoshi

  Waseda University

• Goto Satoshi

  Waseda Univ. Jpn

• Goto Satoshi

  Graduate School Of Information Production And Systems Waseda University

• Peng Xiao

  Waseda Univ. Kitakyushu‐shi Jpn

• Zhou Dajiang

  Waseda Univ. Kitakyushu‐shi Jpn

• Zhao Xiongxin

  Waseda Univ. Kitakyushu‐shi Jpn

• Chen Zhixiang

  Waseda Univ. Kitakyushu‐shi Jpn

• Zhou Dajiang

  Graduate School Of Information Production And Systems Waseda University

• Zhao Xiongxin

  Graduate School Of Information Production And Systems Waseda University

• Chen Zhixiang

  Graduate School Of Information Production And Systems Waseda University

• Peng Xiao

  Graduate School Of Information Production And Systems Waseda University

• Goto Satoshi

  Graduate School Of Information Production And System Waseda University

• Xiongxin Zhao

  School of Information, Production and Systems, Waseda University

• Goto Satoshi

  Graduate School of Infomlation Production and Systems Waseda University

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