Low-Power Partial Distortion Sorting Fast Motion Estimation Algorithms and VLSI Implementations(<Special Section>Advanced Image Technology)
スポンサーリンク
概要
- 論文の詳細を見る
This paper presents two hardware-friendly low-power oriented fast motion estimation (ME) algorithms and their VLSI implementations. The basic idea of the proposed partial distortion sorting (PDS) algorithm is to disable the search points which have larger partial distortions during the ME process, and only keep those search points with smaller ones. To further reduce the computation overhead, a simplified local PDS (LPDS) algorithm is also presented. Experiments show that the PDS and LPDS algorithms can provide almost the same image quality as full search only with 36.7% computation complexity. The proposed two algorithms can be integrated into different FSBMA architectures to save power consumption. In this paper, the 1-D inter ME architecture is used as an detailed example. Under the worst working conditions (1.62V, 125℃) and 166MHz clock frequency, the PDS algorithm can reduce 33.3% power consumption with 4.05K gates extra hardware cost, and the LPDS can reduce 37.8% power consumption with 1.73K gates overhead.
- 社団法人電子情報通信学会の論文
- 2007-01-01
著者
-
GOTO Satoshi
Graduate School of Information, Production and Systems, Waseda University
-
Ikenaga Takeshi
Graduate school of Information, Production and Systems, Waseda University
-
Ikenaga Takeshi
Graduate School Of Information Production And System Waseda University
-
Ikenaga Takeshi
Graduate School Of Ips Waseda University
-
SONG Yang
Graduate School of Information, Production and Systems, Waseda University
-
Song Yang
Graduate School Of Ips Waseda University
-
Liu Zhenyu
Kitakyushu Foundation For The Advancement Of Industry Science And Technology
-
Liu Zhenyu
Ips Waseda University
-
Song Yang
Graduate School Of Information Production And Systems Waseda University
-
Goto Satoshi
Graduate School Of Information Production And System Waseda University
-
Liu Zhenyu
Tsinghua University
-
Ikenaga Takeshi
The Graduate School Of Information Production And Systems Waseda University
-
IKENAGA Takeshi
Graduate School of Fundamental Science and Engineering, Waseda University
-
Goto Satoshi
Graduate School of Infomlation Production and Systems Waseda University
関連論文
- Permutation Network for Reconfigurable LDPC Decoder Based on Banyan Network
- 8x8 transformation based all zero block detection for H.264/AVC encoder
- A-4-35 Constant Quality One-Pass Rate Control Algorithm in H.264/AVC
- BS-12-19 A Fast Block Type Decision Algorithm for H.264/AVC Intra Prediction(BS-12. Network Planning, Control, and Management)
- D-11-50 A Novel Fast Block Type Decision Algorithm for Intra Prediction in H.264/AVC High Profile
- D-11-14 A Mode Reduction Based Fast Integer Motion Estimation Algorithm for HDTV
- A-16-2 A Fast Mode Decision Algorithm for H.264/AVC Intra Prediction
- A novel fast block type decision algorithm for intra prediction in H.264/AVC high profile (第21回 回路とシステム軽井沢ワークショップ論文集) -- (動画像符号化(1))
- 8x8 Transformation Based All Zero Block Detection for H.264/AVC Encoder
- Expression and Characterization of Human Rheumatoid Factor Single-Chain FV
- A LOW-POWER AND PERFORMANCE-AWARE DVB-S2 LDPC DECODER WITH LAYERED SCHEDULING
- Region-of-Interest based Preprocessing for H.264/AVC Encoding
- A Macroblock Homogeneity Detection Method and its Application for Block Size Decision in H.264/AVC
- Fast Inter Mode Decision Algorithm Based on Residual Feature
- Turbo decoding based on LDPC message passing algorithm
- Pipeline-Based Partition Exploration for Heterogeneous Multiprocessor Synthesis
- Efficient Fully-Parallel LDPC Decoder Design with Improved Simplified Min-Sum Algorithms(VLSI Architecture for Communication/Server Systems,VLSI Technology toward Frontiers of New Market)
- Power-Efficient LDPC Decoder Architecture Based on Accelerated Message-Passing Schedule(VLSI Architecture,VLSI Design and CAD Algorithms)
- Partially-Parallel LDPC Decoder Achieving High-Efficiency Message-Passing Schedule(Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
- Reconfigurable Adaptive FEC System Based on Reed-Solomon Code with Interleaving(Adaptive Signal Processing, Recent Advances in Circuits and Systems-Part 1)
- BS-12-18 A Novel Hardware-Friendly Regular 3-Step Integer Motion Estimation Algorithm for H.264/AVC(BS-12. Network Planning, Control, and Management)
- A-16-11 Level C+ Bandwidth Reduction Method for MPEG-2 to H.264 Transcoding
- A-16-1 Group-Based Prediction Scheme on Multiple Reference Frame Fractional Motion Estimation in H.264/AVC
- A Sorting-based Architecture of Finding the First Two Minimum Values
- Multiple Likelihood Models based Particle Filter for Long-term Full Occlusion
- Lossless VLSI Oriented Full Computation Reusing Algorithm for H.264/AVC Fractional Motion Estimation(Selected Papers from the 19th Workshop on Circuits and Systems in Karuizawa)
- D-11-70 Adaptive Spatial EC based on Numerical Measures of Edge Statistical Model
- An adaptive error concealment order in H.264/AVC (VLSI設計技術)
- An adaptive error concealment order in H.264/AVC (集積回路)
- D-11-18 An Edge Information Based Block Size Decision Method for Intra Mode Decision in H.264/AVC
- D-11-19 Multi-Stage Based Inter Mode Decision Algorithm in H.264/AVC
- D-11-21 Macroblock Level Rate Control for H.264/AVC Based on Model Parameter Update and Weighted Reference Calculation
- D-11-20 Bayesian Decision Based All-Zero Block Detection Algorithm in H.264/AVC
- A-4-15 Cross Low Pass Filter Based Subsampling Algorithm for H.264/AVC Motion Estimation
- BS-12-20 VLSI Design of Level C Bandwidth Reduction Scheme for MPEG-2 to H.264/AVC Transcoding(BS-12. Network Planning, Control, and Management)
- Lossy Strict Multilevel Successive Elimination Algorithm for Fast Motion Estimation(Selected Papers from the 19th Workshop on Circuits and Systems in Karuizawa)
- Low-Power Partial Distortion Sorting Fast Motion Estimation Algorithms and VLSI Implementations(Advanced Image Technology)
- Motion content based search range prediction in variable block size motion estimation (第20回 回路とシステム軽井沢ワークショップ論文集) -- (映像応用)
- A Fine-Grain Scalable and Low Memory Cost Variable Block Size Motion Estimation Architecture for H.264/AVC(Integrated Electronics)
- A VLSI Architecture for Variable Block Size Motion Estimation in H.264/AVC with Low Cost Memory Organization(VLSI Architecture,VLSI Design and CAD Algorithms)
- Scalable VLSI Architecture for Variable Block Size Integer Motion Estimation in H.264/AVC(Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
- 261MHz Parallel Tree Architecture for Full Search Variable Block Size Motion Estimation in H.264/AVC
- 261MHz Parallel Tree Architecture for Full Search Variable Block Size Motion Estimation in H.264/AVC
- A strict successive elimination algorithm for fast motion estimation (映像信号処理)
- A VLSI Array Processing Oriented Fast Fourier Transform Algorithm and Hardware Implementation(VLSI Architecture, VLSI Design and CAD Algorithms)
- Geometrical, Physical and Text/Symbol Analysis Based Approach of Traffic Sign Detection System(Advanced Image Technology)
- A Highly Parallel Architecture for Deblocking Filter in H.264/AVC(Parallel and/or Distributed Processing Systems, Recent Advances in Circuits and Systems-Part1)
- A low-cost LSI design of AES against DPA attack by hiding power information (第21回 回路とシステム軽井沢ワークショップ論文集) -- (実現技術)
- D-12-69 1D-based 2D Gaussian Convolution Unit Based Hardware Accelerator for Gassian & DoG Pyramid Construction in SIFT
- D-12-95 A GMM based Foreground Extraction Algorithm in Complex Background for Surveillance System
- Low Power LDPC Code Decoder Architecture Based on Intermediate Message Compression Technique
- A 41mW VGA【triple bond】fps Quadtree Video Encoder for Video Surveillance Systems
- Standard Deviation and Intra Prediction Mode Based Adaptive Spatial Error Concealment (SEC) in H.264/AVC
- A high-parallelism reconfigurable permutation network for IEEE 802.11n/803.16e LDPC decoder (情報理論)
- An Irregular Search Window Reuse Scheme for MPEG-2 to H.264 Transcoding
- Pipeline-Based Partition Exploration for Heterogeneous Multiprocessor Synthesis
- Exploring Partitions Based on Search Space Smoothing for Heterogeneous Multiprocessor System
- Fast Custom Instruction Identification Algorithm Based on Basic Convex Pattern Model for Supporting ASIP Automated Design
- Permutation Network for Reconfigurable LDPC Decoder Based on Banyan Network
- Implementation of LDPC decoder for 802.16e (情報理論)
- An multi-rate LDPC decoder system on FPGA (情報理論)
- D-11-21 Low complexity decoding with frame-skipping for surveillance video
- An Efficient Motion Vector Coding Scheme Based on Prioritized Reference Decision
- A High Performance and Low Bandwidth Multi-Standard Motion Compensation Design for HD Video Decoder
- A 48 Cycles/MB H.264/AVC Deblocking Filter Architecture for Ultra High Definition Applications
- A High-Speed Design of Montgomery Multiplier
- Reconfigurable Variable Block Size Motion Estimation Architecture for Search Range Reduction Algorithm
- An Unequal Secure Encryption Scheme for H.264/AVC Video Compression Standard
- D-11-17 MOTION CORRELATION ADAPTION BASED INTER MODE DECISION ALGORITHM FOR H.264/AVC
- High Throughput VLSI Architecture of a Fast Mode Decision Algorithm for H.264/AVC Intra Encoding
- Adaptive Sub-Sampling Based Reconfigurable SAD Tree Architecture for HDTV Application
- Hardware-Oriented Early Detection Algorithms for 4×4 and 8×8 All-Zero Blocks in H.264
- VLSI Oriented Fast Motion Estimation Algorithm Based on Pixel Difference, Block Overlapping and Motion Feature Analysis
- A High Throughput LDPC Decoder Design Based on Novel Delta-value Message-passing Schedule
- A-4-32 Four Pattern Adaptive Down-sampling-Method for Variable Block Size Video Coding
- A Selective Video Encryption Scheme for MPEG Compression Standard(Application, Cryptography and Information Security)
- Adaptive Search Range Algorithms for Variable Block Size Motion Estimation in H.264/AVC
- Content-Aware Fast Motion Estimation for H.264/AVC
- Periodic Spectrum Transmission for Single-Carrier Transmission Frequency-Domain Equalization(Wireless Communication Technologies)
- A-5-34 Closed Form Expression for Bit Error Rate Performance of UWB Signal in the Presence of Inter-Symbol Interference
- A High Performance Partially-Parallel Irregular LDPC Decoder Based on Sum-Delta Message Passing Schedule
- D-11-15 A Novel Three-Step Error Concealment Method for H.264/AVC
- A Bandwidth Optimized, 64 Cycles/MB Joint Parameter Decoder Architecture for Ultra High Definition H.264/AVC Applications
- An Ultra-Low Bandwidth Design Method for MPEG-2 to H.264/AVC Transcoding
- Voltage and Level-Shifter Assignment Driven Floorplanning
- A-6-12 Prediction-based Center-bias Fast Fractional Motion Estimation Algorithm for H.264/AVC
- Generic Permutation Network for QC-LDPC Decoder
- D-11-20 An Adaptive Reference Frame Compression Scheme for Video Decoding
- ROI based Computational Complexity Reduction Scheme for H.264/AVC Encoder
- Multiple Region-of-Interest Based H.264 Encoder with a Detection Architecture in Macroblock Level Pipelining
- A 530Mpixels/s Intra Prediction Architecture for Ultra High Definition H.264/AVC Encoder
- Greedy Optimization Algorithm for the Power/Ground Network Design to Satisfy the Voltage Drop Constraint
- Cache Based Motion Compensation Architecture for Quad-HD H.264/AVC Video Decoder
- A 115mW 1Gbps QC-LDPC Decoder ASIC for WiMAX in 65nm CMOS
- A 98GMACs/W 32-Core Vector Processor in 65nm CMOS
- A 6.72-Gb/s 8 pJ/bit/iteration IEEE 802.15.3c LDPC Decoder Chip
- Greedy Algorithm for the On-Chip Decoupling Capacitance Optimization to Satisfy the Voltage Drop Constraint
- A 115mW 1Gbps QC-LDPC Decoder ASIC for WiMAX in 65nm CMOS
- Cluster Generation and Network Component Insertion for Topology Synthesis of Application-Specific Network-on-Chips
- Correlated Noise Reduction for Electromagnetic Analysis