Liu Zhenyu | Ips Waseda University

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概要

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著作論文

Lossless VLSI Oriented Full Computation Reusing Algorithm for H.264/AVC Fractional Motion Estimation(Selected Papers from the 19th Workshop on Circuits and Systems in Karuizawa)
Lossy Strict Multilevel Successive Elimination Algorithm for Fast Motion Estimation(Selected Papers from the 19th Workshop on Circuits and Systems in Karuizawa)
Low-Power Partial Distortion Sorting Fast Motion Estimation Algorithms and VLSI Implementations(Advanced Image Technology)
A Fine-Grain Scalable and Low Memory Cost Variable Block Size Motion Estimation Architecture for H.264/AVC(Integrated Electronics)
A VLSI Architecture for Variable Block Size Motion Estimation in H.264/AVC with Low Cost Memory Organization(VLSI Architecture,VLSI Design and CAD Algorithms)
Scalable VLSI Architecture for Variable Block Size Integer Motion Estimation in H.264/AVC(Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
261MHz Parallel Tree Architecture for Full Search Variable Block Size Motion Estimation in H.264/AVC
A strict successive elimination algorithm for fast motion estimation (映像信号処理)
A VLSI Array Processing Oriented Fast Fourier Transform Algorithm and Hardware Implementation(VLSI Architecture, VLSI Design and CAD Algorithms)
Content-Aware Fast Motion Estimation for H.264/AVC
Parallel Improved HDTV720p Targeted Propagate Partial SAD Architecture for Variable Block Size Motion Estimation in H.264/AVC
Inter search mode reduction based parallel propagate partial SAD architecture for variable block size motion estimation in H.264/AVC (第20回回路とシステム軽井沢ワークショップ論文集) -- (映像応用)
Loss free VLSI oriented full computation reusing algorithm for H.264 fractional motion estimation (映像信号処理)
Architecture and Circuit Optimization of Hardwired Integer Motion Estimation Engine for H.264/AVC
A Novel Cache Replacement Policy via Dynamic Adaptive Insertion and Re-Reference Prediction

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