A Novel Cache Replacement Policy via Dynamic Adaptive Insertion and Re-Reference Prediction
スポンサーリンク
概要
- 論文の詳細を見る
Previous research illustrates that LRU replacement policy is not efficient when applications exhibit a distant re-reference interval. Recently RRIP policy is proposed to improve the performance for such kind of workloads. However, the lack of access recency information in RRIP confuses the replacement policy to make the accurate prediction. To enhance the robustness of RRIP for recency-friendly workloads, we propose an Dynamic Adaptive Insertion and Re-reference Prediction (DAI-RRP) policy which evicts data based on both re-reference prediction value and the access recency information. DAI-RRP makes adaptive adjustment on insertion position and prediction value for different access patterns, which makes the policy robust across different workloads and different phases. Simulation results show that DAI-RRP outperforms LRU and RRIP. For a single-core processor with a 1MB 16-way set last-level cache (LLC), DAI-RRP reduces CPI over LRU and Dynamic RRIP by an average of 8.1% and 2.7% respectively. Evaluations on quad-core CMP with a 4MB shared LLC show that DAI-RRP outperforms LRU and Dynamic RRIP (DRRIP) on the weighted speedup metric by an average of 8.1% and 15.7% respectively. Furthermore, compared to LRU, DAI-RRP consumes the similar hardware for 16-way cache, or even less hardware for high-associativity cache. In summary, the proposed policy is practical and can be easily integrated into existing hardware approximations of LRU.
- （社）電子情報通信学会の論文
- 2011-04-01
著者
-
Ikenaga Takeshi
Graduate School Of Information Production And System Waseda University
-
Ikenaga Takeshi
Graduate School Of Ips Waseda University
-
Ikenaga Takeshi
Ips Waseda University
-
Ishikawa Tatsuyuki
Graduate School Of Information Production And Systems Waseda University
-
IKENAGA Takeshi
The Graduate School of Information, Production and Systems, Waseda University
-
Liu Zhenyu
Ips Waseda University
-
Liu Zhenyu
Tsinghua University
-
WANG Dongsheng
Tsinghua University
-
Liu Zhenyu
Tsinghua National Laboratory For Information Science And Technology And Department Of Computer Scien
-
ZHANG Xi
Tsinghua National Laboratory for Information Science and Technology, and Department of Computer Scie
-
LI Chongmin
Tsinghua National Laboratory for Information Science and Technology, and Department of Computer Scie
-
WANG Haixia
Tsinghua National Laboratory for Information Science and Technology, and Department of Computer Scie
-
Wang Haixia
Tsinghua National Laboratory For Information Science And Technology And Department Of Computer Scien
-
Wang Dongsheng
Tsinghua National Laboratory For Information Science And Technology And Department Of Computer Scien
-
Zhang Xi
Tsinghua National Laboratory For Information Science And Technology And Department Of Computer Scien
-
Li Chongmin
Tsinghua National Laboratory For Information Science And Technology And Department Of Computer Scien
-
IKENAGA Takeshi
Graduate School of Fundamental Science and Engineering, Waseda University
関連論文
- BS-12-19 A Fast Block Type Decision Algorithm for H.264/AVC Intra Prediction(BS-12. Network Planning, Control, and Management)
- D-11-50 A Novel Fast Block Type Decision Algorithm for Intra Prediction in H.264/AVC High Profile
- D-11-14 A Mode Reduction Based Fast Integer Motion Estimation Algorithm for HDTV
- A-16-2 A Fast Mode Decision Algorithm for H.264/AVC Intra Prediction
- A novel fast block type decision algorithm for intra prediction in H.264/AVC high profile (第21回 回路とシステム軽井沢ワークショップ論文集) -- (動画像符号化(1))
- 8x8 Transformation Based All Zero Block Detection for H.264/AVC Encoder
- Expression and Characterization of Human Rheumatoid Factor Single-Chain FV
- Efficient Fully-Parallel LDPC Decoder Design with Improved Simplified Min-Sum Algorithms(VLSI Architecture for Communication/Server Systems,VLSI Technology toward Frontiers of New Market)
- Power-Efficient LDPC Decoder Architecture Based on Accelerated Message-Passing Schedule(VLSI Architecture,VLSI Design and CAD Algorithms)
- Partially-Parallel LDPC Decoder Achieving High-Efficiency Message-Passing Schedule(Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
- Reconfigurable Adaptive FEC System Based on Reed-Solomon Code with Interleaving(Adaptive Signal Processing, Recent Advances in Circuits and Systems-Part 1)
- BS-12-18 A Novel Hardware-Friendly Regular 3-Step Integer Motion Estimation Algorithm for H.264/AVC(BS-12. Network Planning, Control, and Management)
- A-16-11 Level C+ Bandwidth Reduction Method for MPEG-2 to H.264 Transcoding
- A-16-1 Group-Based Prediction Scheme on Multiple Reference Frame Fractional Motion Estimation in H.264/AVC
- Multiple Likelihood Models based Particle Filter for Long-term Full Occlusion
- Lossless VLSI Oriented Full Computation Reusing Algorithm for H.264/AVC Fractional Motion Estimation(Selected Papers from the 19th Workshop on Circuits and Systems in Karuizawa)
- D-11-70 Adaptive Spatial EC based on Numerical Measures of Edge Statistical Model
- An adaptive error concealment order in H.264/AVC (VLSI設計技術)
- An adaptive error concealment order in H.264/AVC (集積回路)
- D-11-18 An Edge Information Based Block Size Decision Method for Intra Mode Decision in H.264/AVC
- D-11-19 Multi-Stage Based Inter Mode Decision Algorithm in H.264/AVC
- D-11-21 Macroblock Level Rate Control for H.264/AVC Based on Model Parameter Update and Weighted Reference Calculation
- D-11-20 Bayesian Decision Based All-Zero Block Detection Algorithm in H.264/AVC
- A-4-15 Cross Low Pass Filter Based Subsampling Algorithm for H.264/AVC Motion Estimation
- BS-12-20 VLSI Design of Level C Bandwidth Reduction Scheme for MPEG-2 to H.264/AVC Transcoding(BS-12. Network Planning, Control, and Management)
- Lossy Strict Multilevel Successive Elimination Algorithm for Fast Motion Estimation(Selected Papers from the 19th Workshop on Circuits and Systems in Karuizawa)
- Low-Power Partial Distortion Sorting Fast Motion Estimation Algorithms and VLSI Implementations(Advanced Image Technology)
- Motion content based search range prediction in variable block size motion estimation (第20回 回路とシステム軽井沢ワークショップ論文集) -- (映像応用)
- A Fine-Grain Scalable and Low Memory Cost Variable Block Size Motion Estimation Architecture for H.264/AVC(Integrated Electronics)
- A VLSI Architecture for Variable Block Size Motion Estimation in H.264/AVC with Low Cost Memory Organization(VLSI Architecture,VLSI Design and CAD Algorithms)
- Scalable VLSI Architecture for Variable Block Size Integer Motion Estimation in H.264/AVC(Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
- 261MHz Parallel Tree Architecture for Full Search Variable Block Size Motion Estimation in H.264/AVC
- 261MHz Parallel Tree Architecture for Full Search Variable Block Size Motion Estimation in H.264/AVC
- A strict successive elimination algorithm for fast motion estimation (映像信号処理)
- A VLSI Array Processing Oriented Fast Fourier Transform Algorithm and Hardware Implementation(VLSI Architecture, VLSI Design and CAD Algorithms)
- Geometrical, Physical and Text/Symbol Analysis Based Approach of Traffic Sign Detection System(Advanced Image Technology)
- A Contour-Based Robust Algorithm for Text Detection in Color Images(Image Recognition, Computer Vision)
- Content-Based Complexity Reduction Methods for MPEG-2 to H.264 Transcoding(Advanced Image Technology)
- A Hardware Implementation of a Content-Based Motion Estimation Algorithm for Real-Time MPEG-4 Video Coding(Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
- A Highly Parallel Architecture for Deblocking Filter in H.264/AVC(Parallel and/or Distributed Processing Systems, Recent Advances in Circuits and Systems-Part1)
- Content-Based Motion Estimation with Extended Temporal-Spatial Analysis(Image Processing and Multimedia Systems, Recent Advances in Circuits and Systems-Part 1)
- A low-cost LSI design of AES against DPA attack by hiding power information (第21回 回路とシステム軽井沢ワークショップ論文集) -- (実現技術)
- An efficient encryption scheme for H.264 format video streams (第20回 回路とシステム軽井沢ワークショップ論文集) -- (画像応用)
- A high-speed design of Montgomery multiplier (第20回 回路とシステム軽井沢ワークショップ論文集) -- (システム実現技術)
- D-12-69 1D-based 2D Gaussian Convolution Unit Based Hardware Accelerator for Gassian & DoG Pyramid Construction in SIFT
- D-12-95 A GMM based Foreground Extraction Algorithm in Complex Background for Surveillance System
- Low Power LDPC Code Decoder Architecture Based on Intermediate Message Compression Technique
- A 41mW VGA【triple bond】fps Quadtree Video Encoder for Video Surveillance Systems
- Standard Deviation and Intra Prediction Mode Based Adaptive Spatial Error Concealment (SEC) in H.264/AVC
- Variable Block Size Motion Vector Retrieval Schemes for H.264 Inter Frame Error Concealment
- Highly Parallel Fractional Motion Estimation Engine for Super Hi-Vision 4k×4k@60fps
- A High-Speed Design of Montgomery Multiplier
- Reconfigurable Variable Block Size Motion Estimation Architecture for Search Range Reduction Algorithm
- An Unequal Secure Encryption Scheme for H.264/AVC Video Compression Standard
- High Throughput VLSI Architecture of a Fast Mode Decision Algorithm for H.264/AVC Intra Encoding
- Adaptive Sub-Sampling Based Reconfigurable SAD Tree Architecture for HDTV Application
- Hardware-Oriented Early Detection Algorithms for 4×4 and 8×8 All-Zero Blocks in H.264
- VLSI Oriented Fast Motion Estimation Algorithm Based on Pixel Difference, Block Overlapping and Motion Feature Analysis
- Macroblock Feature Based Complexity Reduction for H.264/AVC Motion Estimation
- A High Throughput LDPC Decoder Design Based on Novel Delta-value Message-passing Schedule
- Macroblock and Motion Feature Analysis to H.264/AVC Fast Inter Mode Decision
- A Selective Video Encryption Scheme for MPEG Compression Standard(Application, Cryptography and Information Security)
- Adaptive Search Range Algorithms for Variable Block Size Motion Estimation in H.264/AVC
- Content-Aware Fast Motion Estimation for H.264/AVC
- Edge Block Detection and Motion Vector Information Based Fast VBSME Algorithm
- Parallel Improved HDTV720p Targeted Propagate Partial SAD Architecture for Variable Block Size Motion Estimation in H.264/AVC
- A-4-18 Integer Search Position Based Fast Motion Estimation in H.264/AVC
- Inter search mode reduction based parallel propagate partial SAD architecture for variable block size motion estimation in H.264/AVC (第20回 回路とシステム軽井沢ワークショップ論文集) -- (映像応用)
- Constant Bit-Rate Multi-Stage Rate Control for Rate-Distortion Optimized H.264/AVC Encoders
- A High Performance Partially-Parallel Irregular LDPC Decoder Based on Sum-Delta Message Passing Schedule
- A-4-33 High Throughput Rate-1/2 Partially-Parallel Irregular LDPC Decoder
- Loss free VLSI oriented full computation reusing algorithm for H.264 fractional motion estimation (映像信号処理)
- An Ultra-Low Bandwidth Design Method for MPEG-2 to H.264/AVC Transcoding
- A-6-12 Prediction-based Center-bias Fast Fractional Motion Estimation Algorithm for H.264/AVC
- Architecture and Circuit Optimization of Hardwired Integer Motion Estimation Engine for H.264/AVC
- Scale invariance based salient contour detection (「膨大化する画像データのための高度画像入出力技術」[画像電子]学会創立35周年記念論文特集号)
- Highly Parallel and Fully Reused H.264/AVC High Profile Intra Predictor Generation Engine for Super Hi-Vision 4k×4k@60fps
- A Novel Cache Replacement Policy via Dynamic Adaptive Insertion and Re-Reference Prediction
- Fast H.264/AVC DIRECT Mode Decision Based on Mode Selection and Predicted Rate-Distortion Cost
- Content Based Coarse to Fine Adaptive Interpolation Filter for High Resolution Video Coding
- Low-Complexity Coarse-Level Mode-Mapping Based H.264/AVC to H.264/SVC Spatial Transcoding for Video Conferencing
- A Drift-Constrained Frequency-Domain Ultra-Low-Delay H.264/SVC to H.264/AVC Transcoder with Medium-Grain Quality Scalability for Videoconferencing
- Content-Aware Write Reduction Mechanism of 3D Stacked Phase-Change RAM Based Frame Store in H.264 Video Codec System